genode/base/include/platform/pbxa9/drivers/board.h
Martin Stein 8d03312528 base_hw: Use board-specific 'Core_tlb'.
'Core_tlb' ensures that core never throws pagefaults,
in contrast to its base 'Tlb' that is planned to use displacement
in the future.

'Core_tlb' enables the application of differenet memory attributes
in core, according to the board specific partitioning of the physical
address space. This way it enables caching in core.
2012-11-14 16:36:51 +01:00

73 lines
1.5 KiB
C++

/**
* \brief Driver for the Realview PBXA9 board
* \author Martin stein
* \date 2011-11-03
*/
/*
* Copyright (C) 2011-2012 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__DRIVERS__BOARD_H_
#define _INCLUDE__DRIVERS__BOARD_H_
namespace Genode
{
/**
* Driver for the Realview PBXA9 board
*/
struct Board
{
enum
{
/* normal RAM */
RAM_0_BASE = 0x00000000,
RAM_0_SIZE = 0x10000000,
RAM_1_BASE = 0x20000000,
RAM_1_SIZE = 0x10000000,
/* device IO memory */
MMIO_0_BASE = 0x10000000,
MMIO_0_SIZE = 0x10000000,
MMIO_1_BASE = 0x4e000000,
MMIO_1_SIZE = 0x01000000,
NORTHBRIDGE_AHB_BASE = 0x10020000,
NORTHBRIDGE_AHB_SIZE = 768*1024,
/* southbridge */
SOUTHBRIDGE_APB_BASE = 0x10000000,
SOUTHBRIDGE_APB_SIZE = 128*1024,
/* clocks */
OSC_6_CLOCK = 24*1000*1000,
OSC_7_CLOCK = 14*1000*1000,
/* CPU */
CORTEX_A9_CLOCK = OSC_7_CLOCK * 5,
CORTEX_A9_PRIVATE_MEM_BASE = 0x1f000000,
CORTEX_A9_PRIVATE_MEM_SIZE = 0x01000000,
/* UART */
PL011_0_MMIO_BASE = 0x10009000,
PL011_0_MMIO_SIZE = 0x00001000,
PL011_0_CLOCK = OSC_6_CLOCK,
PL011_0_IRQ = 44,
/* timer */
SP804_0_1_MMIO_BASE = 0x10011000,
SP804_0_1_MMIO_SIZE = 0x00001000,
SP804_0_1_IRQ = 36,
SP804_0_1_CLOCK = 1000*1000,
SECURITY_EXTENSION = 0,
};
};
}
#endif /* _INCLUDE__DRIVERS__BOARD_H_ */