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base_hw: Use board-specific 'Core_tlb'.

Browse Source 
'Core_tlb' ensures that core never throws pagefaults,
in contrast to its base 'Tlb' that is planned to use displacement
in the future.

'Core_tlb' enables the application of differenet memory attributes
in core, according to the board specific partitioning of the physical
address space. This way it enables caching in core.
This commit is contained in:
Martin Stein 2012-11-07 15:12:56 +01:00 committed by Norman Feske
parent 4d2a3de0ee
commit 8d03312528
17 changed files with 328 additions and 116 deletions
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2
base-hw/src/core/imx31/platform_support.cc
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@ -25,7 +25,7 @@ Native_region * Platform::_ram_regions(unsigned const i)
{
static Native_region _regions[] =
{
{ Board::CSD0_SDRAM_BASE, Board::CSD0_SDRAM_SIZE }
{ Board::RAM_0_BASE, Board::RAM_0_SIZE }
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}

32
base-hw/src/core/imx31/tlb.h
View File

@ -16,11 +16,39 @@
/* Genode includes */
#include <arm/v6/section_table.h>
#include <drivers/board.h>
/**
* Software TLB controls
* Software TLB-controls
*/
class Tlb : public Arm_v6::Section_table { };
class Tlb : public Arm_v6::Section_table
{
public:
/**
* Placement new
*/
void * operator new (Genode::size_t, void * p) { return p; }
};
/**
* TLB of core
*
* Must ensure that core never gets a pagefault.
*/
class Core_tlb : public Tlb
{
public:
Core_tlb()
{
/* map RAM */
translate_dpm_off(Board::RAM_0_BASE, Board::RAM_0_SIZE, 0, 1);
/* map MMIO */
translate_dpm_off(Board::MMIO_0_BASE, Board::MMIO_0_SIZE, 1, 0);
}
};
#endif /* _SRC__CORE__IMX31__TLB_H_ */

73
base-hw/src/core/include/arm/section_table.h
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@ -232,9 +232,10 @@ namespace Arm
struct Small_page : Descriptor
{
enum {
VIRT_SIZE_LOG2 = _4KB_LOG2,
VIRT_SIZE = 1 << VIRT_SIZE_LOG2,
VIRT_BASE_MASK = ~((1 << VIRT_SIZE_LOG2) - 1)
VIRT_SIZE_LOG2 = _4KB_LOG2,
VIRT_SIZE = 1 << VIRT_SIZE_LOG2,
VIRT_OFFSET_MASK = (1 << VIRT_SIZE_LOG2) - 1,
VIRT_BASE_MASK = ~(VIRT_OFFSET_MASK),
};
struct Xn : Bitfield<0, 1> { }; /* execute never */
@ -442,6 +443,22 @@ namespace Arm
return true;
}
/**
* Get next translation size log2 by area constraints
*
* \param vo virtual offset within this table
* \param s area size
*/
static unsigned
translation_size_l2(addr_t const vo, size_t const s)
{
off_t const o = vo & Small_page::VIRT_OFFSET_MASK;
if (!o && s >= Small_page::VIRT_SIZE)
return Small_page::VIRT_SIZE_LOG2;
PDBG("Insufficient alignment or size");
while (1) ;
}
} __attribute__((aligned(1<<Page_table::ALIGNM_LOG2)));
/**
@ -575,9 +592,10 @@ namespace Arm
struct Section : Descriptor
{
enum {
VIRT_SIZE_LOG2 = _1MB_LOG2,
VIRT_SIZE = 1 << VIRT_SIZE_LOG2,
VIRT_BASE_MASK = ~((1 << VIRT_SIZE_LOG2) - 1)
VIRT_SIZE_LOG2 = _1MB_LOG2,
VIRT_SIZE = 1 << VIRT_SIZE_LOG2,
VIRT_OFFSET_MASK = (1 << VIRT_SIZE_LOG2) - 1,
VIRT_BASE_MASK = ~(VIRT_OFFSET_MASK),
};
struct B : Bitfield<2, 1> { }; /* mem. region attr. */
@ -877,6 +895,49 @@ namespace Arm
}
return false;
}
/**
* Get next translation size log2 by area constraints
*
* \param vo virtual offset within this table
* \param s area size
*/
static unsigned
translation_size_l2(addr_t const vo, size_t const s)
{
off_t const o = vo & Section::VIRT_OFFSET_MASK;
if (!o && s >= Section::VIRT_SIZE)
return Section::VIRT_SIZE_LOG2;
return Page_table::translation_size_l2(o, s);
}
/**
* Insert translations for given area, do not permit displacement
*
* \param vo virtual offset within this table
* \param s area size
* \param d wether area maps device IO memory
* \param c wether area maps cacheable memory
*/
template <typename ST>
void translate_dpm_off(addr_t vo, size_t s,
bool const d, bool const c, ST * st)
{
unsigned tsl2 = translation_size_l2(vo, s);
size_t ts = 1 << tsl2;
while (1) {
if(st->insert_translation(vo, vo, tsl2, 1,1,0,0,d,c)) {
PDBG("Displacement not permitted");
return;
}
vo += ts;
s = ts < s ? s - ts : 0;
if (!s) break;
tsl2 = translation_size_l2(vo, s);
ts = 1 << tsl2;
}
}
} __attribute__((aligned(1<<Section_table::ALIGNM_LOG2)));
}

15
base-hw/src/core/include/arm/v6/section_table.h
View File

@ -82,6 +82,21 @@ namespace Arm_v6
x, k, g, d, c, this,
extra_space);
}
/**
* Insert translations for given area, do not permit displacement
*
* \param vo virtual offset within this table
* \param s area size
* \param d wether area maps device IO memory
* \param c wether area maps cacheable memory
*/
void translate_dpm_off(addr_t vo, size_t s,
bool const d, bool const c)
{
Arm::Section_table::
translate_dpm_off<Section_table>(vo, s, d, c, this);
}
};
}

15
base-hw/src/core/include/arm/v7/section_table.h
View File

@ -98,6 +98,21 @@ namespace Arm_v7
extra_space);
}
/**
* Insert translations for given area, do not permit displacement
*
* \param vo virtual offset within this table
* \param s area size
* \param d wether area maps device IO memory
* \param c wether area maps cacheable memory
*/
void translate_dpm_off(addr_t vo, size_t s,
bool const d, bool const c)
{
Arm::Section_table::
translate_dpm_off<Section_table>(vo, s, d, c, this);
}
/***************
** Accessors **
***************/

67
base-hw/src/core/kernel.cc
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@ -782,33 +782,12 @@ namespace Kernel
static Mode_transition_control * mtc()
{ static Mode_transition_control _object; return &_object; }
/**
* Ensures that PDs align their TLB data for hardware table walks
*/
class Pd_base
{
Tlb _tlb;
public:
/**
* Alignment that instances of this class need
*/
static unsigned alignm_log2() { return Tlb::ALIGNM_LOG2; }
/***************
** Accessors **
***************/
Tlb * tlb() { return &_tlb; }
};
/**
* Kernel object that represents a Genode PD
*/
class Pd : public Pd_base,
public Object<Pd, MAX_PDS>
class Pd : public Object<Pd, MAX_PDS>
{
Tlb * const _tlb;
/* keep ready memory for size aligned extra costs at construction */
enum { EXTRA_SPACE_SIZE = 2*Tlb::MAX_COSTS_PER_TRANSLATION };
@ -819,7 +798,7 @@ namespace Kernel
/**
* Constructor
*/
Pd()
Pd(Tlb * const t) : _tlb(t)
{
/* try to add translation for mode transition region */
enum Mtc_attributes { W = 1, X = 1, K = 1, G = 1, D = 0, C = 1 };
@ -859,6 +838,12 @@ namespace Kernel
c->protection_domain(id());
c->tlb(tlb()->base());
}
/***************
** Accessors **
***************/
Tlb * tlb() { return _tlb; }
};
/**
@ -1113,7 +1098,12 @@ namespace Kernel
/**
* Static kernel PD that describes core
*/
static Pd * core() { static Pd _object; return &_object; }
static Pd * core()
{
static Core_tlb tlb;
static Pd _pd(&tlb);
return &_pd;
}
/**
@ -1543,10 +1533,10 @@ namespace Kernel
* Get attributes of the kernel objects
*/
size_t thread_size() { return sizeof(Thread); }
size_t pd_size() { return sizeof(Pd); }
size_t pd_size() { return sizeof(Tlb) + sizeof(Pd); }
size_t signal_context_size() { return sizeof(Signal_context); }
size_t signal_receiver_size() { return sizeof(Signal_receiver); }
unsigned pd_alignm_log2() { return Pd::alignm_log2(); }
unsigned pd_alignm_log2() { return Tlb::ALIGNM_LOG2; }
size_t vm_size() { return sizeof(Vm); }
@ -1618,9 +1608,11 @@ namespace Kernel
/* check permissions */
assert(user->pd_id() == core_id());
/* create PD */
/* create TLB and PD */
void * dst = (void *)user->user_arg_1();
Pd * const pd = new (dst) Pd();
Tlb * const tlb = new (dst) Tlb();
dst = (void *)((addr_t)dst + sizeof(Tlb));
Pd * const pd = new (dst) Pd(tlb);
/* return success */
user->user_arg_0(pd->id());
@ -2122,23 +2114,6 @@ extern "C" void kernel()
/* kernel initialization */
} else {
/* compose core address space */
addr_t a = 0;
while (1)
{
/* map everything except the mode transition region */
enum {
SIZE_LOG2 = Tlb::MAX_PAGE_SIZE_LOG2,
SIZE = 1 << SIZE_LOG2,
};
if (mtc()->VIRT_END <= a || mtc()->VIRT_BASE > (a + SIZE - 1))
assert(!core()->tlb()->insert_translation(a, a, SIZE_LOG2,
1, 1, 0, 0, 1, 0));
/* check condition to continue */
addr_t const next_a = a + SIZE;
if (next_a > a) a = next_a;
else break;
}
/* compose kernel CPU context */
static Cpu::Context kernel_context;
kernel_context.ip = (addr_t)kernel;

7
base-hw/src/core/panda_a2/platform_support.cc
View File

@ -26,8 +26,7 @@ Native_region * Platform::_ram_regions(unsigned const i)
{
static Native_region _regions[] =
{
{ Board::EMIF1_EMIF2_CS0_SDRAM_BASE,
Board::EMIF1_EMIF2_CS0_SDRAM_SIZE }
{ Board::RAM_0_BASE, Board::RAM_0_SIZE }
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}
@ -61,8 +60,8 @@ Native_region * Platform::_mmio_regions(unsigned const i)
{
static Native_region _regions[] =
{
{ Board::L4_PER_BASE, Board::L4_PER_SIZE },
{ Board::L4_CFG_BASE, Board::L4_CFG_SIZE },
{ Board::MMIO_0_BASE, Board::MMIO_0_SIZE },
{ Board::MMIO_1_BASE, Board::MMIO_1_SIZE },
{ Board::DSS_MMIO_BASE, Board::DSS_MMIO_SIZE },
{ Board::DISPC_MMIO_BASE, Board::DISPC_MMIO_SIZE },
{ Board::HDMI_MMIO_BASE, Board::HDMI_MMIO_SIZE }

37
base-hw/src/core/panda_a2/tlb.h
View File

@ -15,12 +15,45 @@
#define _SRC__CORE__PANDA_A2__TLB_H_
/* Genode includes */
#include <drivers/board.h>
/* core includes */
#include <arm/v7/section_table.h>
/**
* Software TLB controls
* Software TLB-controls
*/
class Tlb : public Arm_v7::Section_table { };
class Tlb : public Arm_v7::Section_table
{
public:
/**
* Placement new
*/
void * operator new (Genode::size_t, void * p) { return p; }
};
/**
* TLB of core
*
* Must ensure that core never gets a pagefault.
*/
class Core_tlb : public Tlb
{
public:
Core_tlb()
{
using namespace Genode;
/* map RAM */
translate_dpm_off(Board::RAM_0_BASE, Board::RAM_0_SIZE, 0, 1);
/* map MMIO */
translate_dpm_off(Board::MMIO_0_BASE, Board::MMIO_0_SIZE, 1, 0);
translate_dpm_off(Board::MMIO_1_BASE, Board::MMIO_1_SIZE, 1, 0);
}
};
#endif /* _SRC__CORE__PANDA_A2__TLB_H_ */

7
base-hw/src/core/pbxa9/platform_support.cc
View File

@ -27,7 +27,8 @@ Native_region * Platform::_ram_regions(unsigned const i)
{
static Native_region _regions[] =
{
{ Board::NORTHBRIDGE_DDR_0_BASE, Board::NORTHBRIDGE_DDR_0_SIZE }
{ Board::RAM_0_BASE, Board::RAM_0_SIZE },
{ Board::RAM_1_BASE, Board::RAM_1_SIZE }
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}
@ -61,8 +62,8 @@ Native_region * Platform::_mmio_regions(unsigned const i)
{
static Native_region _regions[] =
{
{ Board::SOUTHBRIDGE_APB_BASE, Board::SOUTHBRIDGE_APB_SIZE },
{ Board::NORTHBRIDGE_AHB_BASE, Board::NORTHBRIDGE_AHB_SIZE }
{ Board::MMIO_0_BASE, Board::MMIO_0_SIZE },
{ Board::MMIO_1_BASE, Board::MMIO_1_SIZE }
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}

38
base-hw/src/core/pbxa9/tlb.h
View File

@ -14,13 +14,47 @@
#ifndef _SRC__CORE__PBXA9__TLB_H_
#define _SRC__CORE__PBXA9__TLB_H_
/* Genode includes */
#include <drivers/board.h>
/* core includes */
#include <arm/v7/section_table.h>
/**
* Software TLB controls
* Software TLB-controls
*/
class Tlb : public Arm_v7::Section_table { };
class Tlb : public Arm_v7::Section_table
{
public:
/**
* Placement new
*/
void * operator new (Genode::size_t, void * p) { return p; }
};
/**
* TLB of core
*
* Must ensure that core never gets a pagefault.
*/
class Core_tlb : public Tlb
{
public:
Core_tlb()
{
using namespace Genode;
/* map RAM */
translate_dpm_off(Board::RAM_0_BASE, Board::RAM_0_SIZE, 0, 1);
translate_dpm_off(Board::RAM_1_BASE, Board::RAM_1_SIZE, 0, 1);
/* map MMIO */
translate_dpm_off(Board::MMIO_0_BASE, Board::MMIO_0_SIZE, 1, 0);
translate_dpm_off(Board::MMIO_1_BASE, Board::MMIO_1_SIZE, 1, 0);
}
};
#endif /* _SRC__CORE__PBXA9__TLB_H_ */

9
base-hw/src/core/vea9x4/platform_support.cc
View File

@ -26,7 +26,10 @@ Native_region * Platform::_ram_regions(unsigned const i)
{
static Native_region _regions[] =
{
{ Board::LOCAL_DDR2_BASE, Board::LOCAL_DDR2_SIZE }
{ Board::RAM_0_BASE, Board::RAM_0_SIZE },
{ Board::RAM_1_BASE, Board::RAM_1_SIZE },
{ Board::RAM_2_BASE, Board::RAM_2_SIZE },
{ Board::RAM_3_BASE, Board::RAM_3_SIZE }
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}
@ -60,8 +63,8 @@ Native_region * Platform::_mmio_regions(unsigned const i)
{
static Native_region _regions[] =
{
{ Board::SMB_CS7_BASE, Board::SMB_CS7_SIZE },
{ Board::SMB_CS0_TO_CS6_BASE, Board::SMB_CS0_TO_CS6_SIZE }
{ Board::MMIO_0_BASE, Board::MMIO_0_SIZE },
{ Board::MMIO_1_BASE, Board::MMIO_1_SIZE },
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}

42
base-hw/src/core/vea9x4/tlb.h
View File

@ -1,5 +1,5 @@
/*
* \brief Software TLB controls specific for the Versatile VEA9X4
* \brief SW controls for the translation lookaside-buffer
* \author Martin Stein
* \date 2012-04-23
*/
@ -15,12 +15,48 @@
#define _SRC__CORE__VEA9X4__TLB_H_
/* Genode includes */
#include <drivers/board.h>
/* core includes */
#include <arm/v7/section_table.h>
/**
* Software TLB controls
* Software TLB-controls
*/
class Tlb : public Arm_v7::Section_table { };
class Tlb : public Arm_v7::Section_table
{
public:
/**
* Placement new
*/
void * operator new (Genode::size_t, void * p) { return p; }
};
/**
* TLB of core
*
* Must ensure that core never gets a pagefault.
*/
class Core_tlb : public Tlb
{
public:
Core_tlb()
{
using namespace Genode;
/* map RAM */
translate_dpm_off(Board::RAM_0_BASE, Board::RAM_0_SIZE, 0, 1);
translate_dpm_off(Board::RAM_1_BASE, Board::RAM_1_SIZE, 0, 1);
translate_dpm_off(Board::RAM_2_BASE, Board::RAM_2_SIZE, 0, 1);
translate_dpm_off(Board::RAM_3_BASE, Board::RAM_3_SIZE, 0, 1);
/* map MMIO */
translate_dpm_off(Board::MMIO_0_BASE, Board::MMIO_0_SIZE, 1, 0);
translate_dpm_off(Board::MMIO_1_BASE, Board::MMIO_1_SIZE, 1, 0);
}
};
#endif /* _SRC__CORE__VEA9X4__TLB_H_ */

8
base-hw/src/core/vea9x4/trustzone/platform_support.cc
View File

@ -26,7 +26,7 @@ Native_region * Platform::_ram_regions(unsigned const i)
{
static Native_region _regions[] =
{
{ Board::SRAM_BASE, Board::SRAM_SIZE }
{ Board::RAM_3_BASE, Board::RAM_3_SIZE }
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}
@ -63,9 +63,9 @@ Native_region * Platform::_mmio_regions(unsigned const i)
{
static Native_region _regions[] =
{
{ Board::SMB_CS7_BASE, Board::SMB_CS7_SIZE },
{ Board::SMB_CS0_TO_CS6_BASE, Board::SMB_CS0_TO_CS6_SIZE },
{ Board::LOCAL_DDR2_BASE, Board::LOCAL_DDR2_SIZE },
{ Board::MMIO_0_BASE, Board::MMIO_0_SIZE },
{ Board::MMIO_1_BASE, Board::MMIO_1_SIZE },
{ 0x60000000, 0x40000000 },
{ Board::TZASC_MMIO_BASE, Board::TZASC_MMIO_SIZE },
{ Board::TZPC_MMIO_BASE, Board::TZPC_MMIO_SIZE },
};

7
base/include/platform/imx31/drivers/board.h
View File

@ -26,8 +26,11 @@ namespace Genode
struct Board
{
enum {
CSD0_SDRAM_BASE = 0x80000000,
CSD0_SDRAM_SIZE = 0x10000000,
RAM_0_BASE = 0x80000000,
RAM_0_SIZE = 0x20000000,
MMIO_0_BASE = 0x30000000,
MMIO_0_SIZE = 0x50000000,
UART_1_IRQ = 45,
UART_1_MMIO_BASE = 0x43f90000,

30
base/include/platform/panda_a2/drivers/board.h
View File

@ -23,37 +23,37 @@ namespace Genode
{
enum
{
/* interconnect domains */
L4_PER_BASE = 0x48000000,
L4_PER_SIZE = 0x01000000,
L4_CFG_BASE = 0x4a000000,
L4_CFG_SIZE = 0x01000000,
/* device IO memory */
MMIO_0_BASE = 0x48000000,
MMIO_0_SIZE = 0x01000000,
MMIO_1_BASE = 0x4a000000,
MMIO_1_SIZE = 0x01000000,
/* normal RAM */
RAM_0_BASE = 0x80000000,
RAM_0_SIZE = 0x40000000,
/* clocks */
MPU_DPLL_CLOCK = 200*1000*1000,
/* UART */
TL16C750_3_MMIO_BASE = L4_PER_BASE + 0x20000,
TL16C750_3_MMIO_SIZE = 0x2000,
TL16C750_3_MMIO_BASE = 0x48020000,
TL16C750_3_MMIO_SIZE = 0x00002000,
TL16C750_3_CLOCK = 48*1000*1000,
TL16C750_3_IRQ = 74,
/* CPU */
CORTEX_A9_PRIVATE_MEM_BASE = L4_PER_BASE + 0x240000,
CORTEX_A9_PRIVATE_MEM_SIZE = 0x2000,
CORTEX_A9_PRIVATE_MEM_BASE = 0x48240000,
CORTEX_A9_PRIVATE_MEM_SIZE = 0x00002000,
CORTEX_A9_CLOCK = MPU_DPLL_CLOCK,
/* RAM */
EMIF1_EMIF2_CS0_SDRAM_BASE = 0x80000000,
EMIF1_EMIF2_CS0_SDRAM_SIZE = 0x40000000,
/* display subsystem */
DSS_MMIO_BASE = 0x58000000,
DSS_MMIO_SIZE = 0x00001000,
DISPC_MMIO_BASE = 0x58001000,
DISPC_MMIO_SIZE = 0x1000,
DISPC_MMIO_SIZE = 0x00001000,
HDMI_MMIO_BASE = 0x58006000,
HDMI_MMIO_SIZE = 0x1000,
HDMI_MMIO_SIZE = 0x00001000,
/* misc */
SECURITY_EXTENSION = 0,

22
base/include/platform/pbxa9/drivers/board.h
View File

@ -23,9 +23,17 @@ namespace Genode
{
enum
{
/* northbridge */
NORTHBRIDGE_DDR_0_BASE = 0x00000000, /* DMC mirror */
NORTHBRIDGE_DDR_0_SIZE = 256*1024*1024,
/* normal RAM */
RAM_0_BASE = 0x00000000,
RAM_0_SIZE = 0x10000000,
RAM_1_BASE = 0x20000000,
RAM_1_SIZE = 0x10000000,
/* device IO memory */
MMIO_0_BASE = 0x10000000,
MMIO_0_SIZE = 0x10000000,
MMIO_1_BASE = 0x4e000000,
MMIO_1_SIZE = 0x01000000,
NORTHBRIDGE_AHB_BASE = 0x10020000,
NORTHBRIDGE_AHB_SIZE = 768*1024,
@ -44,14 +52,14 @@ namespace Genode
CORTEX_A9_PRIVATE_MEM_SIZE = 0x01000000,
/* UART */
PL011_0_MMIO_BASE = SOUTHBRIDGE_APB_BASE + 0x9000,
PL011_0_MMIO_SIZE = 4*1024,
PL011_0_MMIO_BASE = 0x10009000,
PL011_0_MMIO_SIZE = 0x00001000,
PL011_0_CLOCK = OSC_6_CLOCK,
PL011_0_IRQ = 44,
/* timer */
SP804_0_1_MMIO_BASE = SOUTHBRIDGE_APB_BASE + 0x11000,
SP804_0_1_MMIO_SIZE = 4*1024,
SP804_0_1_MMIO_BASE = 0x10011000,
SP804_0_1_MMIO_SIZE = 0x00001000,
SP804_0_1_IRQ = 36,
SP804_0_1_CLOCK = 1000*1000,

33
base/include/platform/vea9x4/drivers/board.h
View File

@ -25,21 +25,30 @@ namespace Genode
{
enum
{
/* static memory bus */
SMB_CS2_BASE = 0x48000000,
SMB_CS7_BASE = 0x10000000,
SMB_CS7_SIZE = 0x20000,
SMB_CS0_TO_CS6_BASE = 0x40000000,
SMB_CS0_TO_CS6_SIZE = 0x20000000,
/* MMIO */
MMIO_0_BASE = 0x10000000,
MMIO_0_SIZE = 0x10000000,
MMIO_1_BASE = 0x4C000000,
MMIO_1_SIZE = 0x04000000,
/* RAM */
RAM_0_BASE = 0x00000000,
RAM_0_SIZE = 0x04000000,
RAM_1_BASE = 0x60000000,
RAM_1_SIZE = 0x20000000,
RAM_2_BASE = 0x84000000,
RAM_2_SIZE = 0x1c000000,
RAM_3_BASE = 0x48000000,
RAM_3_SIZE = 0x01ffffff,
/* UART */
PL011_0_MMIO_BASE = SMB_CS7_BASE + 0x9000,
PL011_0_MMIO_BASE = MMIO_0_BASE + 0x9000,
PL011_0_MMIO_SIZE = 0x1000,
PL011_0_CLOCK = 24*1000*1000,
PL011_0_IRQ = 5,
/* timer/counter */
SP804_0_1_MMIO_BASE = SMB_CS7_BASE + 0x11000,
SP804_0_1_MMIO_BASE = MMIO_0_BASE + 0x11000,
SP804_0_1_MMIO_SIZE = 0x1000,
SP804_0_1_CLOCK = 1000*1000,
SP804_0_1_IRQ = 34,
@ -60,14 +69,6 @@ namespace Genode
CORTEX_A9_PRIVATE_MEM_SIZE = 0x2000,
CORTEX_A9_CLOCK = TCREF_CLOCK,
/* RAM */
LOCAL_DDR2_BASE = 0x60000000,
LOCAL_DDR2_SIZE = 0x40000000,
/* SRAM */
SRAM_BASE = SMB_CS2_BASE,
SRAM_SIZE = 0x01ffffff,
SECURITY_EXTENSION = 1,
};
};