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- Enable the "platform-level interrupt controller" PLIC on base-hw - The RISC-V specification offers only a register description, but no layout for the register set. This implies the layout is platform dependent, and therefore, implemented separately for Qemu issue #4042 |
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bootstrap-hw-riscv_qemu.mk | ||
core-hw-riscv_qemu.mk | ||
ld-hw.mk | ||
startup-hw.mk | ||
syscall-hw.mk |