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According to ARM Cortex-A55 Core Technical Reference Manual r1p0 the lowest 8 bits (Aff0) of MPIDR register represent thread IDs within a multi-threaded core. The actual core identification bits are in Aff1. This layout can be identified by checking the MT bit of MPIDR register. Basically, if MT=1 core id is in Aff1, if MT=0 core id is in Aff0. Without this change Genode will identify all CPU cores on A55 as primary (0) core. Its worth to mention that Cortex-A55 by itself is not a multi-threaded CPU. Aff0 values are always expected to be 0 for pure A55 cores. A55 cores can however be paired with cores that are multi-threaded. To support such big.LITTLE CPUs in Genode we'd probably need to add a different mechanism for mapping MPIDR values to logical, contignous core IDs which Genode expects. Ref: https://developer.arm.com/documentation/100442/0100/register-descriptions/aarch64-system-registers/mpidr-el1--multiprocessor-affinity-register--el1?lang=en |
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