mirror of
https://github.com/genodelabs/genode.git
synced 2024-12-19 05:37:54 +00:00
hw: remove rpi1/3 board support
The code moved to https://github.com/skalk/genode-rpi Ref #4363
This commit is contained in:
parent
f79d5d640f
commit
6bd7f167a4
@ -1 +0,0 @@
|
||||
arm_v6
|
@ -1 +0,0 @@
|
||||
0x00800000
|
@ -1 +0,0 @@
|
||||
arm_v8a
|
@ -1 +0,0 @@
|
||||
0x00800000
|
@ -1,8 +0,0 @@
|
||||
REP_INC_DIR += src/bootstrap/board/rpi
|
||||
|
||||
SRC_CC += bootstrap/board/rpi/platform.cc
|
||||
SRC_CC += bootstrap/spec/arm/arm_v6_cpu.cc
|
||||
SRC_CC += hw/spec/32bit/memory_map.cc
|
||||
SRC_S += bootstrap/spec/arm/crt0.s
|
||||
|
||||
include $(call select_from_repositories,lib/mk/bootstrap-hw.inc)
|
@ -1,18 +0,0 @@
|
||||
#
|
||||
# \brief Build config for Genodes core process
|
||||
# \author Norman Feske
|
||||
# \date 2013-04-05
|
||||
#
|
||||
|
||||
# add include paths
|
||||
REP_INC_DIR += src/core/board/rpi
|
||||
|
||||
# add C++ sources
|
||||
SRC_CC += platform_services.cc
|
||||
SRC_CC += spec/arm/bcm2835_pic.cc
|
||||
SRC_CC += spec/arm/bcm2835_system_timer.cc
|
||||
|
||||
# include less specific configuration
|
||||
include $(call select_from_repositories,lib/mk/spec/arm_v6/core-hw.inc)
|
||||
|
||||
CC_CXX_WARN_STRICT_CONVERSION =
|
@ -1,20 +0,0 @@
|
||||
#
|
||||
# \brief Build config for Genodes core process
|
||||
# \author Martin Stein
|
||||
# \author Stefan Kalkowski
|
||||
# \date 2012-10-04
|
||||
#
|
||||
|
||||
# add include paths
|
||||
REP_INC_DIR += src/core/spec/arm_v6
|
||||
|
||||
# add C++ sources
|
||||
SRC_CC += spec/arm_v6/perf_counter.cc
|
||||
SRC_CC += kernel/vm_thread_off.cc
|
||||
SRC_CC += kernel/cpu_up.cc
|
||||
SRC_CC += kernel/lock.cc
|
||||
|
||||
SRC_S += spec/arm/vfpv2.s
|
||||
|
||||
# include less specific configuration
|
||||
include $(call select_from_repositories,lib/mk/spec/arm/core-hw.inc)
|
@ -1,13 +0,0 @@
|
||||
REP_INC_DIR += src/bootstrap/board/rpi3
|
||||
|
||||
SRC_CC += bootstrap/spec/arm_64/cortex_a53_mmu.cc
|
||||
SRC_CC += bootstrap/board/rpi3/platform.cc
|
||||
SRC_CC += lib/base/arm_64/kernel/interface.cc
|
||||
SRC_CC += spec/64bit/memory_map.cc
|
||||
SRC_S += bootstrap/spec/arm_64/crt0.s
|
||||
|
||||
NR_OF_CPUS = 4
|
||||
|
||||
vpath spec/64bit/memory_map.cc $(call select_from_repositories,src/lib/hw)
|
||||
|
||||
include $(call select_from_repositories,lib/mk/bootstrap-hw.inc)
|
@ -1,12 +0,0 @@
|
||||
REP_INC_DIR += src/core/board/rpi3
|
||||
|
||||
# add C++ sources
|
||||
SRC_CC += kernel/vm_thread_off.cc
|
||||
SRC_CC += platform_services.cc
|
||||
SRC_CC += spec/arm/bcm2835_pic.cc
|
||||
SRC_CC += spec/arm/bcm2837_pic.cc
|
||||
|
||||
NR_OF_CPUS = 4
|
||||
|
||||
# include less specific configuration
|
||||
include $(call select_from_repositories,lib/mk/spec/arm_v8/core-hw.inc)
|
@ -1 +0,0 @@
|
||||
include $(GENODE_DIR)/repos/base-hw/recipes/src/base-hw_content.inc
|
@ -1 +0,0 @@
|
||||
2021-12-16 e34c1b6f62714608fb1d932ce6425ff00906cb67
|
@ -1,2 +0,0 @@
|
||||
base-hw
|
||||
base
|
@ -1 +0,0 @@
|
||||
include $(GENODE_DIR)/repos/base-hw/recipes/src/base-hw_content.inc
|
@ -1 +0,0 @@
|
||||
2021-12-16 c886e168d012a5dda38b1b933deedbe03a8cac4f
|
@ -1,2 +0,0 @@
|
||||
base-hw
|
||||
base
|
@ -1,32 +0,0 @@
|
||||
/*
|
||||
* \brief Raspberry PI specific board definitions
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2017-02-20
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _SRC__BOOTSTRAP__SPEC__RPI__BOARD_H_
|
||||
#define _SRC__BOOTSTRAP__SPEC__RPI__BOARD_H_
|
||||
|
||||
#include <hw/spec/arm/rpi_board.h>
|
||||
#include <hw/spec/arm/page_table.h>
|
||||
#include <spec/arm/cpu.h>
|
||||
|
||||
namespace Board { using namespace Hw::Rpi_board; }
|
||||
|
||||
|
||||
constexpr unsigned Hw::Page_table::Descriptor_base::_device_tex() { return 0; }
|
||||
|
||||
|
||||
constexpr bool Hw::Page_table::Descriptor_base::_smp() { return false; }
|
||||
|
||||
|
||||
void Hw::Page_table::_table_changed(unsigned long, unsigned long) { }
|
||||
|
||||
#endif /* _SRC__BOOTSTRAP__SPEC__RPI__BOARD_H_ */
|
@ -1,92 +0,0 @@
|
||||
/*
|
||||
* \brief Platform implementations specific for base-hw and Raspberry Pi
|
||||
* \author Norman Feske
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2013-04-05
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2013-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#include <hw/assert.h>
|
||||
#include <platform.h>
|
||||
|
||||
using namespace Rpi;
|
||||
|
||||
|
||||
/**
|
||||
* Leave out the first page (being 0x0) from bootstraps RAM allocator,
|
||||
* some code does not feel happy with addresses being zero
|
||||
*/
|
||||
Bootstrap::Platform::Board::Board()
|
||||
:
|
||||
early_ram_regions(Memory_region { RAM_0_BASE + 0x1000,
|
||||
RAM_0_SIZE - 0x1000 }),
|
||||
late_ram_regions(Memory_region { RAM_0_BASE, 0x1000 }),
|
||||
core_mmio(Memory_region { PL011_0_MMIO_BASE,
|
||||
PL011_0_MMIO_SIZE },
|
||||
Memory_region { SYSTEM_TIMER_MMIO_BASE,
|
||||
SYSTEM_TIMER_MMIO_SIZE },
|
||||
Memory_region { IRQ_CONTROLLER_BASE,
|
||||
IRQ_CONTROLLER_SIZE },
|
||||
Memory_region { USB_DWC_OTG_BASE,
|
||||
USB_DWC_OTG_SIZE })
|
||||
{ }
|
||||
|
||||
|
||||
unsigned Bootstrap::Platform::enable_mmu()
|
||||
{
|
||||
using ::Board::Cpu;
|
||||
|
||||
Cpu::Sctlr::init();
|
||||
|
||||
Cpu::Cpsr::init();
|
||||
|
||||
struct Ctr : Cpu::Ctr
|
||||
{
|
||||
struct P : Bitfield<23, 1> { }; /* page mapping restriction on */
|
||||
};
|
||||
|
||||
/* check for mapping restrictions */
|
||||
assert(!Ctr::P::get(Cpu::Ctr::read()));
|
||||
|
||||
/* invalidate TLB */
|
||||
Cpu::Tlbiall::write(0);
|
||||
|
||||
/* address space ID to zero */
|
||||
Cpu::Cidr::write(0);
|
||||
|
||||
/* do not use domains, but permission bits in table */
|
||||
Cpu::Dacr::write(Cpu::Dacr::D0::bits(1));
|
||||
|
||||
Cpu::Ttbcr::write(1);
|
||||
|
||||
Genode::addr_t table = (Genode::addr_t)core_pd->table_base;
|
||||
Cpu::Ttbr::access_t ttbr = Cpu::Ttbr::init(table);
|
||||
Cpu::Ttbr0::write(ttbr);
|
||||
Cpu::Ttbr1::write(ttbr);
|
||||
|
||||
struct Sctlr : Cpu::Sctlr
|
||||
{
|
||||
struct U : Bitfield<22,1> { }; /* enable unaligned data access */
|
||||
struct Xp : Bitfield<23,1> { }; /* disable subpage AP bits */
|
||||
};
|
||||
|
||||
Cpu::Sctlr::access_t sctlr = Cpu::Sctlr::read();
|
||||
Cpu::Sctlr::C::set(sctlr, 1);
|
||||
Cpu::Sctlr::I::set(sctlr, 1);
|
||||
Sctlr::U::set(sctlr, 1);
|
||||
Sctlr::Xp::set(sctlr, 1);
|
||||
Cpu::Sctlr::Z::set(sctlr, 1);
|
||||
Cpu::Sctlr::M::set(sctlr, 1);
|
||||
Cpu::Sctlr::write(sctlr);
|
||||
|
||||
/* invalidate branch predictor */
|
||||
Cpu::Bpiall::write(0);
|
||||
|
||||
return 0;
|
||||
}
|
@ -1,33 +0,0 @@
|
||||
/*
|
||||
* \brief Board driver for bootstrap
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2019-05-10
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2019 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _BOOTSTRAP__SPEC__RPI3__BOARD_H_
|
||||
#define _BOOTSTRAP__SPEC__RPI3__BOARD_H_
|
||||
|
||||
#include <hw/spec/arm_64/rpi3_board.h>
|
||||
#include <hw/spec/arm_64/cpu.h>
|
||||
#include <hw/spec/arm/lpae.h>
|
||||
|
||||
namespace Board {
|
||||
|
||||
using namespace Hw::Rpi3_board;
|
||||
|
||||
struct Cpu : Hw::Arm_64_cpu
|
||||
{
|
||||
static void wake_up_all_cpus(void*);
|
||||
};
|
||||
|
||||
struct Pic { }; /* dummy object */
|
||||
};
|
||||
|
||||
#endif /* _BOOTSTRAP__SPEC__RPI3__BOARD_H_ */
|
@ -1,50 +0,0 @@
|
||||
/*
|
||||
* \brief Platform implementations specific for base-hw and Raspberry Pi3
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2019-05-11
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2019 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#include <platform.h>
|
||||
|
||||
/**
|
||||
* Leave out the first page (being 0x0) from bootstraps RAM allocator,
|
||||
* some code does not feel happy with addresses being zero
|
||||
*/
|
||||
Bootstrap::Platform::Board::Board()
|
||||
:
|
||||
early_ram_regions(Memory_region { ::Board::RAM_BASE + 0x1000,
|
||||
::Board::RAM_SIZE - 0x1000 }),
|
||||
late_ram_regions(Memory_region { ::Board::RAM_BASE, 0x1000 }),
|
||||
core_mmio(Memory_region { ::Board::UART_BASE, ::Board::UART_SIZE },
|
||||
Memory_region { ::Board::LOCAL_IRQ_CONTROLLER_BASE,
|
||||
::Board::LOCAL_IRQ_CONTROLLER_SIZE },
|
||||
Memory_region { ::Board::IRQ_CONTROLLER_BASE,
|
||||
::Board::IRQ_CONTROLLER_SIZE },
|
||||
Memory_region { ::Board::USB_DWC_OTG_BASE,
|
||||
::Board::USB_DWC_OTG_SIZE })
|
||||
{ }
|
||||
|
||||
|
||||
extern unsigned int _crt0_qemu_start_secondary_cpus;
|
||||
|
||||
|
||||
void Board::Cpu::wake_up_all_cpus(void * ip)
|
||||
{
|
||||
/* start when in qemu */
|
||||
_crt0_qemu_start_secondary_cpus = 1;
|
||||
|
||||
/* start on real hardware */
|
||||
*((void * volatile *) 0xe0) = ip; /* cpu 1 */
|
||||
*((void * volatile *) 0xe8) = ip; /* cpu 2 */
|
||||
*((void * volatile *) 0xf0) = ip; /* cpu 3 */
|
||||
|
||||
/* send event for both variants */
|
||||
asm volatile("dsb #15; sev");
|
||||
}
|
@ -1,31 +0,0 @@
|
||||
/*
|
||||
* \brief Board driver for core
|
||||
* \author Martin Stein
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2012-04-23
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2012-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _CORE__SPEC__RPI__BOARD_H_
|
||||
#define _CORE__SPEC__RPI__BOARD_H_
|
||||
|
||||
/* base-hw internal includes */
|
||||
#include <hw/spec/arm/rpi_board.h>
|
||||
|
||||
/* base-hw Core includes */
|
||||
#include <spec/arm/bcm2835_pic.h>
|
||||
#include <spec/arm/bcm2835_system_timer.h>
|
||||
#include <spec/arm_v6/cpu.h>
|
||||
|
||||
namespace Board {
|
||||
using namespace Hw::Rpi_board;
|
||||
class Pic : public Bcm2835_pic { };
|
||||
};
|
||||
|
||||
#endif /* _CORE__SPEC__RPI__BOARD_H_ */
|
@ -1,33 +0,0 @@
|
||||
/*
|
||||
* \brief Board driver for core
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2019-05-10
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2019 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _CORE__SPEC__RPI3__BOARD_H_
|
||||
#define _CORE__SPEC__RPI3__BOARD_H_
|
||||
|
||||
/* base-hw internal includes */
|
||||
#include <hw/spec/arm_64/rpi3_board.h>
|
||||
|
||||
/* base-hw Core includes */
|
||||
#include <spec/arm/bcm2837_pic.h>
|
||||
#include <spec/arm/generic_timer.h>
|
||||
#include <spec/arm_v8/cpu.h>
|
||||
|
||||
namespace Board {
|
||||
|
||||
using namespace Hw::Rpi3_board;
|
||||
class Pic : public Bcm2837_pic { };
|
||||
|
||||
enum { TIMER_IRQ = 1 };
|
||||
};
|
||||
|
||||
#endif /* _CORE__SPEC__RPI3__BOARD_H_ */
|
@ -1,134 +0,0 @@
|
||||
/*
|
||||
* \brief Pic implementation specific to Rpi 1
|
||||
* \author Norman Feske
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2016-01-07
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2016-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#include <board.h>
|
||||
#include <platform.h>
|
||||
|
||||
using namespace Genode;
|
||||
|
||||
|
||||
bool Board::Bcm2835_pic::Usb_dwc_otg::_need_trigger_sof(uint32_t host_frame,
|
||||
uint32_t scheduled_frame)
|
||||
{
|
||||
uint32_t const max_frame = 0x3fff;
|
||||
|
||||
if (host_frame < scheduled_frame) {
|
||||
if (scheduled_frame - host_frame < max_frame / 2)
|
||||
return false; /* scheduled frame not reached yet */
|
||||
else
|
||||
return true; /* scheduled frame passed, host frame wrapped */
|
||||
} else {
|
||||
if (host_frame - scheduled_frame < max_frame / 2)
|
||||
return true; /* scheduled frame passed */
|
||||
else
|
||||
return false; /* scheduled frame wrapped, not reached */
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Board::Bcm2835_pic::
|
||||
Usb_dwc_otg::Usb_dwc_otg(Global_interrupt_controller &global_irq_ctrl)
|
||||
:
|
||||
Mmio { Platform::mmio_to_virt(Board::USB_DWC_OTG_BASE) },
|
||||
_global_irq_ctrl { global_irq_ctrl }
|
||||
{
|
||||
write<Guid::Num>(0);
|
||||
write<Guid::Num_valid>(false);
|
||||
write<Guid::Kick>(false);
|
||||
}
|
||||
|
||||
|
||||
bool Board::Bcm2835_pic::Usb_dwc_otg::handle_sof()
|
||||
{
|
||||
if (!_is_sof())
|
||||
return false;
|
||||
|
||||
if (_global_irq_ctrl.increment_and_return_sof_cnt() == 8*20) {
|
||||
_global_irq_ctrl.reset_sof_cnt();
|
||||
return false;
|
||||
}
|
||||
|
||||
if (!read<Guid::Num_valid>() || read<Guid::Kick>())
|
||||
return false;
|
||||
|
||||
if (_need_trigger_sof(read<Host_frame_number::Num>(),
|
||||
read<Guid::Num>()))
|
||||
return false;
|
||||
|
||||
write<Core_irq_status::Sof>(1);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
Board::Bcm2835_pic::Bcm2835_pic(Global_interrupt_controller &global_irq_ctrl,
|
||||
Genode::addr_t irq_ctrl_base)
|
||||
:
|
||||
Mmio(Platform::mmio_to_virt(irq_ctrl_base ? irq_ctrl_base
|
||||
: (Genode::addr_t) Board::IRQ_CONTROLLER_BASE)),
|
||||
_usb { global_irq_ctrl }
|
||||
{
|
||||
mask();
|
||||
}
|
||||
|
||||
|
||||
bool Board::Bcm2835_pic::take_request(unsigned &irq)
|
||||
{
|
||||
/* read GPU IRQ status mask */
|
||||
uint32_t const p1 = read<Irq_pending_gpu_1>(),
|
||||
p2 = read<Irq_pending_gpu_2>();
|
||||
|
||||
/* search for lowest set bit in pending masks */
|
||||
for (unsigned i = 0; i < NR_OF_IRQ; i++) {
|
||||
|
||||
if (!_is_pending(i, p1, p2))
|
||||
continue;
|
||||
|
||||
irq = i;
|
||||
|
||||
/* handle SOF interrupts locally, filter from the user land */
|
||||
if (irq == Board::DWC_IRQ)
|
||||
if (_usb.handle_sof())
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
void Board::Bcm2835_pic::mask()
|
||||
{
|
||||
write<Irq_disable_basic>(~0);
|
||||
write<Irq_disable_gpu_1>(~0);
|
||||
write<Irq_disable_gpu_2>(~0);
|
||||
}
|
||||
|
||||
|
||||
void Board::Bcm2835_pic::unmask(unsigned const i, unsigned)
|
||||
{
|
||||
if (i < 32) { write<Irq_enable_gpu_1>(1 << i); }
|
||||
else { write<Irq_enable_gpu_2>(1 << (i - 32)); }
|
||||
}
|
||||
|
||||
|
||||
void Board::Bcm2835_pic::mask(unsigned const i)
|
||||
{
|
||||
if (i < 32) { write<Irq_disable_gpu_1>(1 << i); }
|
||||
else { write<Irq_disable_gpu_2>(1 << (i - 32)); }
|
||||
}
|
||||
|
||||
|
||||
void Board::Bcm2835_pic::irq_mode(unsigned, unsigned, unsigned) { }
|
@ -1,144 +0,0 @@
|
||||
/*
|
||||
* \brief Programmable interrupt controller for core
|
||||
* \author Norman Feske
|
||||
* \date 2013-04-05
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2013-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _CORE__SPEC__ARM__BCM2835_PIC_H_
|
||||
#define _CORE__SPEC__ARM__BCM2835_PIC_H_
|
||||
|
||||
/* Genode includes */
|
||||
#include <util/mmio.h>
|
||||
|
||||
namespace Board {
|
||||
|
||||
class Global_interrupt_controller;
|
||||
class Bcm2835_pic;
|
||||
}
|
||||
|
||||
|
||||
class Board::Global_interrupt_controller
|
||||
{
|
||||
private:
|
||||
|
||||
int _sof_cnt { 0 };
|
||||
|
||||
public:
|
||||
|
||||
int increment_and_return_sof_cnt() { return ++_sof_cnt; }
|
||||
|
||||
void reset_sof_cnt() { _sof_cnt = 0; }
|
||||
};
|
||||
|
||||
|
||||
class Board::Bcm2835_pic : Genode::Mmio
|
||||
{
|
||||
public:
|
||||
|
||||
enum {
|
||||
NR_OF_IRQ = 64,
|
||||
|
||||
/*
|
||||
* dummy IPI value on non-SMP platform,
|
||||
* only used in interrupt reservation within generic code
|
||||
*/
|
||||
IPI,
|
||||
};
|
||||
|
||||
private:
|
||||
|
||||
struct Irq_pending_basic : Register<0x0, 32>
|
||||
{
|
||||
struct Timer : Bitfield<0, 1> { };
|
||||
struct Gpu : Bitfield<8, 2> { };
|
||||
};
|
||||
|
||||
struct Irq_pending_gpu_1 : Register<0x04, 32> { };
|
||||
struct Irq_pending_gpu_2 : Register<0x08, 32> { };
|
||||
struct Irq_enable_gpu_1 : Register<0x10, 32> { };
|
||||
struct Irq_enable_gpu_2 : Register<0x14, 32> { };
|
||||
struct Irq_enable_basic : Register<0x18, 32> { };
|
||||
struct Irq_disable_gpu_1 : Register<0x1c, 32> { };
|
||||
struct Irq_disable_gpu_2 : Register<0x20, 32> { };
|
||||
struct Irq_disable_basic : Register<0x24, 32> { };
|
||||
|
||||
class Usb_dwc_otg : Genode::Mmio
|
||||
{
|
||||
private:
|
||||
|
||||
struct Core_irq_status : Register<0x14, 32>
|
||||
{
|
||||
struct Sof : Bitfield<3, 1> { };
|
||||
};
|
||||
|
||||
struct Guid : Register<0x3c, 32>
|
||||
{
|
||||
struct Num : Bitfield<0, 14> { };
|
||||
|
||||
/*
|
||||
* The USB driver set 'Num' to a defined value
|
||||
*/
|
||||
struct Num_valid : Bitfield<31, 1> { };
|
||||
|
||||
/*
|
||||
* Filter is not used, overridden by the USB driver
|
||||
*/
|
||||
struct Kick : Bitfield<30, 1> { };
|
||||
};
|
||||
|
||||
struct Host_frame_number : Register<0x408, 32>
|
||||
{
|
||||
struct Num : Bitfield<0, 14> { };
|
||||
};
|
||||
|
||||
Global_interrupt_controller &_global_irq_ctrl;
|
||||
|
||||
bool _is_sof() const
|
||||
{
|
||||
return read<Core_irq_status::Sof>();
|
||||
}
|
||||
|
||||
static bool _need_trigger_sof(Genode::uint32_t host_frame,
|
||||
Genode::uint32_t scheduled_frame);
|
||||
|
||||
public:
|
||||
|
||||
Usb_dwc_otg(Global_interrupt_controller &global_irq_ctrl);
|
||||
|
||||
bool handle_sof();
|
||||
};
|
||||
|
||||
Usb_dwc_otg _usb;
|
||||
|
||||
/**
|
||||
* Return true if specified interrupt is pending
|
||||
*/
|
||||
static bool _is_pending(unsigned i, Genode::uint32_t p1,
|
||||
Genode::uint32_t p2)
|
||||
{
|
||||
return i < 32 ? (p1 & (1 << i)) : (p2 & (1 << (i - 32)));
|
||||
}
|
||||
|
||||
public:
|
||||
|
||||
Bcm2835_pic(Global_interrupt_controller &global_irq_ctrl,
|
||||
Genode::addr_t irq_ctrl_base = 0);
|
||||
|
||||
bool take_request(unsigned &irq);
|
||||
void finish_request() { }
|
||||
void mask();
|
||||
void unmask(unsigned const i, unsigned);
|
||||
void mask(unsigned const i);
|
||||
void irq_mode(unsigned, unsigned, unsigned);
|
||||
|
||||
static constexpr bool fast_interrupts() { return false; }
|
||||
};
|
||||
|
||||
#endif /* _CORE__SPEC__ARM__BCM2835_PIC_H_ */
|
@ -1,67 +0,0 @@
|
||||
/*
|
||||
* \brief Timer implementation specific to BCM2835 System Timer
|
||||
* \author Norman Feske
|
||||
* \author Stefan Kalkowski
|
||||
* \author Martin Stein
|
||||
* \date 2016-01-07
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2016-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
/* core includes */
|
||||
#include <board.h>
|
||||
#include <platform.h>
|
||||
#include <kernel/timer.h>
|
||||
|
||||
using namespace Genode;
|
||||
using namespace Kernel;
|
||||
using Device = Board::Timer;
|
||||
|
||||
|
||||
Board::Timer::Timer(unsigned)
|
||||
:
|
||||
Mmio(Platform::mmio_to_virt(Board::SYSTEM_TIMER_MMIO_BASE))
|
||||
{ }
|
||||
|
||||
|
||||
void Timer::_start_one_shot(time_t const ticks)
|
||||
{
|
||||
_device.write<Device::Cs::M1>(1);
|
||||
_device.read<Device::Cs>();
|
||||
_device.write<Device::Cmp>(_device.read<Device::Clo>()
|
||||
+ (ticks < 2 ? 2 : ticks));
|
||||
}
|
||||
|
||||
|
||||
enum { TICS_PER_US = Board::SYSTEM_TIMER_CLOCK / 1000 / 1000 };
|
||||
|
||||
|
||||
time_t Timer::ticks_to_us(time_t const ticks) const {
|
||||
return ticks / TICS_PER_US; }
|
||||
|
||||
|
||||
time_t Timer::us_to_ticks(time_t const us) const {
|
||||
return us * TICS_PER_US; }
|
||||
|
||||
|
||||
time_t Timer::_max_value() const {
|
||||
return 0xffffffff; }
|
||||
|
||||
|
||||
time_t Timer::_duration() const
|
||||
{
|
||||
Device::Clo::access_t const clo = _device.read<Device::Clo>();
|
||||
Device::Cmp::access_t const cmp = _device.read<Device::Cmp>();
|
||||
Device::Cs::access_t const irq = _device.read<Device::Cs::M1>();
|
||||
uint32_t d = (irq) ? (uint32_t)_last_timeout_duration + (clo - cmp)
|
||||
: clo - (cmp - _last_timeout_duration);
|
||||
return d;
|
||||
}
|
||||
|
||||
|
||||
unsigned Timer::interrupt_id() const { return Board::SYSTEM_TIMER_IRQ; }
|
@ -1,37 +0,0 @@
|
||||
/*
|
||||
* \brief Timer driver for core
|
||||
* \author Norman Feske
|
||||
* \date 2013-04-05
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2013-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Kernel OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _SRC__CORE__SPEC__ARM__BCM2835_SYSTEM_TIMER_H_
|
||||
#define _SRC__CORE__SPEC__ARM__BCM2835_SYSTEM_TIMER_H_
|
||||
|
||||
/* Kernel includes */
|
||||
#include <util/mmio.h>
|
||||
|
||||
namespace Board { class Timer; }
|
||||
|
||||
|
||||
/**
|
||||
* Timer driver for core
|
||||
*
|
||||
* Timer channel 0 apparently doesn't work on the RPI, so we use channel 1
|
||||
*/
|
||||
struct Board::Timer : Genode::Mmio
|
||||
{
|
||||
struct Cs : Register<0x0, 32> { struct M1 : Bitfield<1, 1> { }; };
|
||||
struct Clo : Register<0x4, 32> { };
|
||||
struct Cmp : Register<0x10, 32> { };
|
||||
|
||||
Timer(unsigned);
|
||||
};
|
||||
|
||||
#endif /* _SRC__CORE__SPEC__ARM__BCM2835_SYSTEM_TIMER_H_ */
|
@ -1,137 +0,0 @@
|
||||
/*
|
||||
* \brief Pic implementation specific to Rpi3
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2019-05-27
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2019 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
/* base-hw Core includes */
|
||||
#include <board.h>
|
||||
#include <platform.h>
|
||||
|
||||
|
||||
Board::Bcm2837_pic::Bcm2837_pic(Global_interrupt_controller &global_irq_ctrl)
|
||||
:
|
||||
Genode::Mmio(Genode::Platform::mmio_to_virt(Board::LOCAL_IRQ_CONTROLLER_BASE)),
|
||||
_bcm2835_pic(global_irq_ctrl, Board::IRQ_CONTROLLER_BASE)
|
||||
{ }
|
||||
|
||||
|
||||
bool Board::Bcm2837_pic::take_request(unsigned & irq)
|
||||
{
|
||||
unsigned cpu = Genode::Cpu::executing_id();
|
||||
Core_irq_source<0>::access_t src = 0;
|
||||
switch (cpu) {
|
||||
case 0: src = read<Core_irq_source<0>>(); break;
|
||||
case 1: src = read<Core_irq_source<1>>(); break;
|
||||
case 2: src = read<Core_irq_source<2>>(); break;
|
||||
case 3: src = read<Core_irq_source<3>>(); break;
|
||||
}
|
||||
|
||||
if ((1 << TIMER_IRQ) & src) {
|
||||
irq = TIMER_IRQ;
|
||||
return true;
|
||||
}
|
||||
|
||||
if (0xf0 & src) {
|
||||
irq = IPI;
|
||||
switch (cpu) {
|
||||
case 0: write<Core_mailbox_clear<0>>(1); break;
|
||||
case 1: write<Core_mailbox_clear<1>>(1); break;
|
||||
case 2: write<Core_mailbox_clear<2>>(1); break;
|
||||
case 3: write<Core_mailbox_clear<3>>(1); break;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
// Gpu interrupt
|
||||
if (cpu == 0 && Core_irq_source<0>::Gpu::get(src)) {
|
||||
auto result = _bcm2835_pic.take_request(irq);
|
||||
return result;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
void Board::Bcm2837_pic::_timer_irq(unsigned cpu, bool enable)
|
||||
{
|
||||
unsigned v = enable ? 1 : 0;
|
||||
switch (cpu) {
|
||||
case 0:
|
||||
write<Core_timer_irq_control<0>::Cnt_p_ns_irq>(v);
|
||||
return;
|
||||
case 1:
|
||||
write<Core_timer_irq_control<1>::Cnt_p_ns_irq>(v);
|
||||
return;
|
||||
case 2:
|
||||
write<Core_timer_irq_control<2>::Cnt_p_ns_irq>(v);
|
||||
return;
|
||||
case 3:
|
||||
write<Core_timer_irq_control<3>::Cnt_p_ns_irq>(v);
|
||||
return;
|
||||
default: ;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void Board::Bcm2837_pic::_ipi(unsigned cpu, bool enable)
|
||||
{
|
||||
unsigned v = enable ? 1 : 0;
|
||||
switch (cpu) {
|
||||
case 0:
|
||||
write<Core_mailbox_irq_control<0>>(v);
|
||||
return;
|
||||
case 1:
|
||||
write<Core_mailbox_irq_control<1>>(v);
|
||||
return;
|
||||
case 2:
|
||||
write<Core_mailbox_irq_control<2>>(v);
|
||||
return;
|
||||
case 3:
|
||||
write<Core_mailbox_irq_control<3>>(v);
|
||||
return;
|
||||
default: ;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void Board::Bcm2837_pic::unmask(unsigned const i, unsigned cpu)
|
||||
{
|
||||
switch (i) {
|
||||
case TIMER_IRQ: _timer_irq(cpu, true); return;
|
||||
case IPI: _ipi(cpu, true); return;
|
||||
}
|
||||
if (cpu == 0) _bcm2835_pic.unmask(i, cpu);
|
||||
}
|
||||
|
||||
|
||||
void Board::Bcm2837_pic::mask(unsigned const i)
|
||||
{
|
||||
unsigned cpu = Genode::Cpu::executing_id();
|
||||
switch (i) {
|
||||
case TIMER_IRQ: _timer_irq(cpu, false); return;
|
||||
case IPI: _ipi(cpu, false); return;
|
||||
}
|
||||
if (cpu == 0) _bcm2835_pic.mask(i);
|
||||
}
|
||||
|
||||
|
||||
void Board::Bcm2837_pic::irq_mode(unsigned, unsigned, unsigned) { }
|
||||
|
||||
|
||||
void Board::Bcm2837_pic::send_ipi(unsigned cpu_target)
|
||||
{
|
||||
switch (cpu_target) {
|
||||
case 0: write<Core_mailbox_set<0>>(1); return;
|
||||
case 1: write<Core_mailbox_set<1>>(1); return;
|
||||
case 2: write<Core_mailbox_set<2>>(1); return;
|
||||
case 3: write<Core_mailbox_set<3>>(1); return;
|
||||
}
|
||||
}
|
@ -1,90 +0,0 @@
|
||||
/*
|
||||
* \brief Programmable interrupt controller for core
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2019-05-27
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2019 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _CORE__SPEC__ARM__BCM2837_PIC_H_
|
||||
#define _CORE__SPEC__ARM__BCM2837_PIC_H_
|
||||
|
||||
#include <util/mmio.h>
|
||||
|
||||
#include <spec/arm/bcm2835_pic.h>
|
||||
|
||||
namespace Board {
|
||||
|
||||
/* Global_interrupt_controller from Bcm2835_pic */
|
||||
class Bcm2837_pic;
|
||||
}
|
||||
|
||||
|
||||
class Board::Bcm2837_pic : Genode::Mmio
|
||||
{
|
||||
public:
|
||||
|
||||
enum {
|
||||
IPI = 0,
|
||||
NR_OF_IRQ = 64,
|
||||
};
|
||||
|
||||
private:
|
||||
|
||||
template <unsigned CPU_NUM>
|
||||
struct Core_timer_irq_control : Register<0x40+CPU_NUM*0x4, 32>
|
||||
{
|
||||
struct Cnt_p_ns_irq
|
||||
: Register<0x40+CPU_NUM*0x4, 32>::template Bitfield<1, 1> {};
|
||||
};
|
||||
|
||||
template <unsigned CPU_NUM>
|
||||
struct Core_mailbox_irq_control : Register<0x50+CPU_NUM*0x4, 32> {};
|
||||
|
||||
template <unsigned CPU_NUM>
|
||||
struct Core_irq_source : Register<0x60+CPU_NUM*0x4, 32> {
|
||||
struct CntPsIrq : Register<0x60+CPU_NUM*0x4, 32>::template Bitfield<0, 1> { };
|
||||
struct CntPnIrq : Register<0x60+CPU_NUM*0x4, 32>::template Bitfield<1, 1> { };
|
||||
struct CntHpIrq : Register<0x60+CPU_NUM*0x4, 32>::template Bitfield<2, 1> { };
|
||||
struct CntVIrq : Register<0x60+CPU_NUM*0x4, 32>::template Bitfield<3, 1> { };
|
||||
struct MBox0 : Register<0x60+CPU_NUM*0x4, 32>::template Bitfield<4, 1> { };
|
||||
struct MBox1 : Register<0x60+CPU_NUM*0x4, 32>::template Bitfield<5, 1> { };
|
||||
struct MBox2 : Register<0x60+CPU_NUM*0x4, 32>::template Bitfield<6, 1> { };
|
||||
struct MBox3 : Register<0x60+CPU_NUM*0x4, 32>::template Bitfield<7, 1> { };
|
||||
struct Gpu : Register<0x60+CPU_NUM*0x4, 32>::template Bitfield<8, 1> { };
|
||||
struct Pmu : Register<0x60+CPU_NUM*0x4, 32>::template Bitfield<9, 1> { };
|
||||
struct Axi : Register<0x60+CPU_NUM*0x4, 32>::template Bitfield<10, 1> { };
|
||||
struct Timer : Register<0x60+CPU_NUM*0x4, 32>::template Bitfield<11, 1> { };
|
||||
};
|
||||
|
||||
template <unsigned CPU_NUM>
|
||||
struct Core_mailbox_set : Register<0x80+CPU_NUM*0x10, 32> {};
|
||||
|
||||
template <unsigned CPU_NUM>
|
||||
struct Core_mailbox_clear : Register<0xc0+CPU_NUM*0x10, 32> {};
|
||||
|
||||
void _ipi(unsigned cpu, bool enable);
|
||||
void _timer_irq(unsigned cpu, bool enable);
|
||||
|
||||
Bcm2835_pic _bcm2835_pic;
|
||||
|
||||
public:
|
||||
|
||||
Bcm2837_pic(Global_interrupt_controller &);
|
||||
|
||||
bool take_request(unsigned &irq);
|
||||
void finish_request() { }
|
||||
void unmask(unsigned const i, unsigned);
|
||||
void mask(unsigned const i);
|
||||
void irq_mode(unsigned, unsigned, unsigned);
|
||||
void send_ipi(unsigned);
|
||||
|
||||
static constexpr bool fast_interrupts() { return false; }
|
||||
};
|
||||
|
||||
#endif /* _CORE__SPEC__ARM__BCM2837_PIC_H_ */
|
@ -1,33 +0,0 @@
|
||||
/*
|
||||
* \brief Raspberry PI specific board definitions
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2019-05-16
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2019 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _SRC__INCLUDE__HW__SPEC__ARM__RPI_BOARD_H_
|
||||
#define _SRC__INCLUDE__HW__SPEC__ARM__RPI_BOARD_H_
|
||||
|
||||
#include <drivers/defs/rpi.h>
|
||||
#include <drivers/uart/pl011.h>
|
||||
#include <hw/spec/arm/boot_info.h>
|
||||
|
||||
namespace Hw::Rpi_board {
|
||||
|
||||
using namespace Rpi;
|
||||
|
||||
using Serial = Genode::Pl011_uart;
|
||||
|
||||
enum {
|
||||
UART_BASE = Rpi::PL011_0_MMIO_BASE,
|
||||
UART_CLOCK = Rpi::PL011_0_CLOCK,
|
||||
};
|
||||
}
|
||||
|
||||
#endif /* _SRC__INCLUDE__HW__SPEC__ARM__RPI_BOARD_H_ */
|
@ -1,46 +0,0 @@
|
||||
/*
|
||||
* \brief Board definitions for Raspberry Pi 3
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2019-05-10
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2019 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _SRC__INCLUDE__HW__SPEC__ARM__RPI3__BOARD_H_
|
||||
#define _SRC__INCLUDE__HW__SPEC__ARM__RPI3__BOARD_H_
|
||||
|
||||
#include <drivers/uart/bcm2835_mini.h>
|
||||
#include <hw/spec/arm/boot_info.h>
|
||||
|
||||
namespace Hw::Rpi3_board {
|
||||
|
||||
using Serial = Genode::Bcm2835_mini_uart;
|
||||
|
||||
enum {
|
||||
RAM_BASE = 0,
|
||||
RAM_SIZE = 0x20000000,
|
||||
|
||||
UART_BASE = 0x3f215000,
|
||||
UART_SIZE = 0x1000,
|
||||
UART_CLOCK = 250000000,
|
||||
|
||||
IRQ_CONTROLLER_BASE = 0x3f00b200,
|
||||
IRQ_CONTROLLER_SIZE = 0x1000,
|
||||
|
||||
LOCAL_IRQ_CONTROLLER_BASE = 0x40000000,
|
||||
LOCAL_IRQ_CONTROLLER_SIZE = 0x1000,
|
||||
|
||||
USB_DWC_OTG_BASE = 0x3f980000,
|
||||
USB_DWC_OTG_SIZE = 0x20000,
|
||||
|
||||
/* USB host controller */
|
||||
DWC_IRQ = 9,
|
||||
};
|
||||
};
|
||||
|
||||
#endif /* _SRC__INCLUDE__HW__SPEC__ARM__RPI3__BOARD_H_ */
|
@ -1 +0,0 @@
|
||||
-M raspi3 -m 1024
|
@ -1,247 +0,0 @@
|
||||
/*
|
||||
* \brief Driver for the MINI UART for Rpi3
|
||||
* \author Tomasz Gajewski
|
||||
* \date 2019-01-30
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2011-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _INCLUDE__DRIVERS__UART__BCM2835_MINI_H_
|
||||
#define _INCLUDE__DRIVERS__UART__BCM2835_MINI_H_
|
||||
|
||||
/* Genode includes */
|
||||
#include <util/mmio.h>
|
||||
|
||||
namespace Genode { class Bcm2835_mini_uart; }
|
||||
|
||||
|
||||
/**
|
||||
* Driver base for the PrimeCell UART MINI Revision r1p3
|
||||
*/
|
||||
class Genode::Bcm2835_mini_uart : Mmio
|
||||
{
|
||||
protected:
|
||||
|
||||
enum { MAX_BAUD_RATE = 0xfffffff };
|
||||
|
||||
/**
|
||||
* Auxiliary Interrupt status
|
||||
*/
|
||||
struct AuxIrq : public Register<0x00, 32>
|
||||
{
|
||||
struct MiniUartIrq : Bitfield<0,1> { }; /* read only */
|
||||
struct Spi1Irq : Bitfield<1,1> { }; /* read only */
|
||||
struct Spi2Irq : Bitfield<2,1> { }; /* read only */
|
||||
};
|
||||
|
||||
/**
|
||||
* Auxiliary enables
|
||||
*/
|
||||
struct AuxEnables : public Register<0x04, 32>
|
||||
{
|
||||
struct MiniUartEnable : Bitfield<0,1> { };
|
||||
struct Spi1Enable : Bitfield<1,1> { };
|
||||
struct Spi2Enable : Bitfield<2,1> { };
|
||||
};
|
||||
|
||||
/**
|
||||
* Mini Uart I/O Data
|
||||
*/
|
||||
struct AuxMuIoReg : public Register<0x40, 32>
|
||||
{
|
||||
struct TransmitReceive : Bitfield<0,8> { };
|
||||
|
||||
struct DLABLS8BitsBaudrate : Bitfield<0,8> { };
|
||||
};
|
||||
|
||||
/**
|
||||
* Mini Uart Interrupt Enable
|
||||
*/
|
||||
struct AuxMuIerReg : public Register<0x44, 32>
|
||||
{
|
||||
struct EnableReceiveInterrupt : Bitfield<0,1> { };
|
||||
struct EnableTransmitInterrupt : Bitfield<1,1> { };
|
||||
|
||||
struct DLABMS8BitsBaudrate : Bitfield<0,8> { };
|
||||
};
|
||||
|
||||
/**
|
||||
* Mini Uart Interrupt Identify
|
||||
*/
|
||||
struct AuxMuIirReg : public Register<0x48, 32>
|
||||
{
|
||||
struct InterruptPending : Bitfield<0,1> { };
|
||||
struct InterruptId : Bitfield<1,2> { /* read only */
|
||||
enum {
|
||||
NO_INTERRUPTS = 0,
|
||||
TRANSMIT_HOLDING_REGISTER_EMPTY = 1,
|
||||
RECEIVER_HOLDS_VALID_BYTE = 2,
|
||||
};
|
||||
|
||||
};
|
||||
struct FifoClear : Bitfield<1,2> { /* write only */
|
||||
enum {
|
||||
CLEAR_RECEIVE_FIFO = 1,
|
||||
CLEAR_TRANSMIT_FIFO = 2,
|
||||
CLEAR_BOTH_FIFOS = 3,
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/**
|
||||
* Mini Uart Line Control
|
||||
*/
|
||||
struct AuxMuLcrReg : public Register<0x4C, 32>
|
||||
{
|
||||
struct DataSize : Bitfield<0,1> { };
|
||||
struct Break : Bitfield<6,1> { };
|
||||
struct DLAB : Bitfield<7,1> { };
|
||||
};
|
||||
|
||||
/**
|
||||
* Mini Uart Modem Control
|
||||
*/
|
||||
struct AuxMuMcrReg : public Register<0x50, 32>
|
||||
{
|
||||
struct RTS : Bitfield<1,1> { };
|
||||
};
|
||||
|
||||
/**
|
||||
* Mini Uart Line Status
|
||||
*/
|
||||
struct AuxMuLsrReg : public Register<0x54, 32>
|
||||
{
|
||||
struct DataReady : Bitfield<0,1> { };
|
||||
struct ReceiverOverrun : Bitfield<1,1> { }; /* read/clear only */
|
||||
struct TransmitterEmpty : Bitfield<5,1> { }; /* read only */
|
||||
struct TransmitterIdle : Bitfield<6,1> { }; /* read only */
|
||||
};
|
||||
|
||||
/**
|
||||
* Mini Uart Modem Status
|
||||
*/
|
||||
struct AuxMuMsrReg : public Register<0x58, 32>
|
||||
{
|
||||
struct CtsStatus : Bitfield<5,1> { }; /* read only */
|
||||
};
|
||||
|
||||
/**
|
||||
* Mini Uart Scratch
|
||||
*/
|
||||
struct AuxMuScratch : public Register<0x5C, 32>
|
||||
{
|
||||
struct Scratch : Bitfield<0,8> { };
|
||||
};
|
||||
|
||||
/**
|
||||
* Mini Uart Extra Control
|
||||
*/
|
||||
struct AuxMuCntlReg : public Register<0x60, 32>
|
||||
{
|
||||
struct ReceiverEnable : Bitfield<0,1> { };
|
||||
struct TransmitterEnable : Bitfield<1,1> { };
|
||||
struct EnableReceiveAutoFlowRTSControl : Bitfield<2,1> { };
|
||||
struct EnableTransmitAutoFlowCTSControl : Bitfield<3,1> { };
|
||||
struct RTSAutoFlowLevel : Bitfield<4,2> {
|
||||
enum {
|
||||
DE_ASSERT_RTS_RECEIVE_FIFO_3 = 0,
|
||||
DE_ASSERT_RTS_RECEIVE_FIFO_2 = 1,
|
||||
DE_ASSERT_RTS_RECEIVE_FIFO_1 = 2,
|
||||
DE_ASSERT_RTS_RECEIVE_FIFO_4 = 3,
|
||||
};
|
||||
};
|
||||
struct RTSAssertLevel : Bitfield<6,1> { };
|
||||
struct CTSAssertLevel : Bitfield<7,1> { };
|
||||
};
|
||||
|
||||
/**
|
||||
* Mini Uart Extra Status
|
||||
*/
|
||||
struct AuxMuStatReg : public Register<0x64, 32>
|
||||
{
|
||||
struct SymbolAvailable : Bitfield<0, 1> { }; /* read only */
|
||||
struct SpaceAvailable : Bitfield<1, 1> { }; /* read only */
|
||||
struct ReceiverIsIdle : Bitfield<2, 1> { }; /* read only */
|
||||
struct TransmitterIsIdle : Bitfield<3, 1> { }; /* read only */
|
||||
struct ReceiverOverrun : Bitfield<4, 1> { }; /* read only */
|
||||
struct TransmitFifoIsFull : Bitfield<5, 1> { }; /* read only */
|
||||
struct RTSStatus : Bitfield<6, 1> { }; /* read only */
|
||||
struct CTSLine : Bitfield<7, 1> { }; /* read only */
|
||||
struct TransmitFifoIsEmpty : Bitfield<8, 1> { }; /* read only */
|
||||
struct TransmitterDone : Bitfield<9, 1> { }; /* read only */
|
||||
struct ReceiveFifoFillLevel : Bitfield<16,4> { }; /* read only */
|
||||
struct TransmitFifoFillLevel : Bitfield<24,4> { }; /* read only */
|
||||
};
|
||||
|
||||
/**
|
||||
* Mini Uart Baudrate
|
||||
*/
|
||||
struct AuxMuBaudReg : public Register<0x68, 32>
|
||||
{
|
||||
struct Baudrate : Bitfield<0,16> { };
|
||||
};
|
||||
|
||||
/**
|
||||
* Idle until the device is ready for action
|
||||
*/
|
||||
void _wait_until_ready() {
|
||||
do {
|
||||
asm volatile("nop");
|
||||
} while (!read<AuxMuLsrReg::TransmitterEmpty>()) ;
|
||||
}
|
||||
|
||||
public:
|
||||
|
||||
/**
|
||||
* Constructor
|
||||
* \param base device MMIO base
|
||||
* \param clock device reference clock frequency
|
||||
* \param baud_rate targeted UART baud rate
|
||||
*/
|
||||
inline Bcm2835_mini_uart(addr_t const base, uint32_t const clock,
|
||||
uint32_t const baud_rate);
|
||||
|
||||
/**
|
||||
* Send ASCII char 'c' over the UART interface
|
||||
*/
|
||||
inline void put_char(char const c);
|
||||
};
|
||||
|
||||
|
||||
Genode::Bcm2835_mini_uart::Bcm2835_mini_uart(addr_t const base,
|
||||
uint32_t const clock,
|
||||
uint32_t const baud_rate)
|
||||
: Mmio(base)
|
||||
{
|
||||
/* enable UART1, AUX mini uart */
|
||||
write<AuxEnables>(read<AuxEnables::MiniUartEnable>() |
|
||||
AuxEnables::MiniUartEnable::bits(1));
|
||||
|
||||
write<AuxMuCntlReg>(0);
|
||||
write<AuxMuLcrReg>(3);
|
||||
write<AuxMuMcrReg>(0);
|
||||
write<AuxMuIerReg>(0);
|
||||
write<AuxMuIirReg>(0xc6);
|
||||
uint32_t const adjusted_br = ((clock / baud_rate) / 8) - 1;
|
||||
write<AuxMuBaudReg>(AuxMuBaudReg::Baudrate::bits(adjusted_br));
|
||||
write<AuxMuCntlReg>(3);
|
||||
_wait_until_ready();
|
||||
}
|
||||
|
||||
|
||||
void Genode::Bcm2835_mini_uart::put_char(char const c)
|
||||
{
|
||||
_wait_until_ready();
|
||||
|
||||
/* transmit character */
|
||||
write<AuxMuIoReg::TransmitReceive>(c);
|
||||
_wait_until_ready();
|
||||
}
|
||||
|
||||
|
||||
#endif /* _INCLUDE__DRIVERS__UART__BCM2835_MINI_H_ */
|
Loading…
Reference in New Issue
Block a user