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https://github.com/genodelabs/genode.git
synced 2024-12-19 05:37:54 +00:00
hw: irq controller and timer improvements for Rpi
* renamed rpi pic to Bcm2835_pic * renamed rpi3 pic to Bcm2837_pic * added bcm2837 control for setting prescaler value (to fix timer_accuracy) * changed handling of all interrupts for rpi3 by cascading to bcm2835 pic * rpi3 irq controller base address made consistent with rpi * added usb controller memory region for pic on rpi3 (for SOF interrupts) Ref #3415
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7db602faec
commit
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@ -3,6 +3,7 @@ REP_INC_DIR += src/core/board/rpi3
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# add C++ sources
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SRC_CC += kernel/vm_thread_off.cc
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SRC_CC += platform_services.cc
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SRC_CC += spec/arm/bcm2835_pic.cc
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SRC_CC += spec/arm/bcm2837_pic.cc
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NR_OF_CPUS = 4
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@ -26,7 +26,9 @@ Bootstrap::Platform::Board::Board()
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Memory_region { ::Board::LOCAL_IRQ_CONTROLLER_BASE,
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::Board::LOCAL_IRQ_CONTROLLER_SIZE },
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Memory_region { ::Board::IRQ_CONTROLLER_BASE,
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::Board::IRQ_CONTROLLER_SIZE })
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::Board::IRQ_CONTROLLER_SIZE },
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Memory_region { ::Board::USB_DWC_OTG_BASE,
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::Board::USB_DWC_OTG_SIZE })
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{ }
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@ -23,6 +23,9 @@
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#include <spec/arm/bcm2835_system_timer.h>
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#include <spec/arm_v6/cpu.h>
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namespace Board { using namespace Hw::Rpi_board; };
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namespace Board {
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using namespace Hw::Rpi_board;
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class Pic : public Bcm2835_pic { };
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};
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#endif /* _CORE__SPEC__RPI__BOARD_H_ */
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@ -25,6 +25,7 @@
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namespace Board {
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using namespace Hw::Rpi3_board;
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class Pic : public Bcm2837_pic { };
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enum { TIMER_IRQ = 1 };
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};
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@ -18,8 +18,8 @@
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using namespace Genode;
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bool Board::Pic::Usb_dwc_otg::_need_trigger_sof(uint32_t host_frame,
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uint32_t scheduled_frame)
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bool Board::Bcm2835_pic::Usb_dwc_otg::_need_trigger_sof(uint32_t host_frame,
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uint32_t scheduled_frame)
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{
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uint32_t const max_frame = 0x3fff;
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@ -37,7 +37,7 @@ bool Board::Pic::Usb_dwc_otg::_need_trigger_sof(uint32_t host_frame,
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}
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Board::Pic::
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Board::Bcm2835_pic::
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Usb_dwc_otg::Usb_dwc_otg(Global_interrupt_controller &global_irq_ctrl)
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:
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Mmio { Platform::mmio_to_virt(Board::USB_DWC_OTG_BASE) },
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@ -49,7 +49,7 @@ Usb_dwc_otg::Usb_dwc_otg(Global_interrupt_controller &global_irq_ctrl)
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}
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bool Board::Pic::Usb_dwc_otg::handle_sof()
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bool Board::Bcm2835_pic::Usb_dwc_otg::handle_sof()
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{
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if (!_is_sof())
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return false;
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@ -72,16 +72,18 @@ bool Board::Pic::Usb_dwc_otg::handle_sof()
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}
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Board::Pic::Pic(Global_interrupt_controller &global_irq_ctrl)
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Board::Bcm2835_pic::Bcm2835_pic(Global_interrupt_controller &global_irq_ctrl,
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Genode::addr_t irq_ctrl_base)
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:
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Mmio { Platform::mmio_to_virt(Board::IRQ_CONTROLLER_BASE) },
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Mmio(Platform::mmio_to_virt(irq_ctrl_base ? irq_ctrl_base
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: (Genode::addr_t) Board::IRQ_CONTROLLER_BASE)),
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_usb { global_irq_ctrl }
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{
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mask();
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}
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bool Board::Pic::take_request(unsigned &irq)
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bool Board::Bcm2835_pic::take_request(unsigned &irq)
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{
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/* read GPU IRQ status mask */
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uint32_t const p1 = read<Irq_pending_gpu_1>(),
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@ -89,6 +91,7 @@ bool Board::Pic::take_request(unsigned &irq)
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/* search for lowest set bit in pending masks */
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for (unsigned i = 0; i < NR_OF_IRQ; i++) {
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if (!_is_pending(i, p1, p2))
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continue;
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@ -106,7 +109,7 @@ bool Board::Pic::take_request(unsigned &irq)
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}
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void Board::Pic::mask()
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void Board::Bcm2835_pic::mask()
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{
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write<Irq_disable_basic>(~0);
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write<Irq_disable_gpu_1>(~0);
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@ -114,18 +117,18 @@ void Board::Pic::mask()
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}
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void Board::Pic::unmask(unsigned const i, unsigned)
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void Board::Bcm2835_pic::unmask(unsigned const i, unsigned)
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{
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if (i < 32) { write<Irq_enable_gpu_1>(1 << i); }
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else { write<Irq_enable_gpu_2>(1 << (i - 32)); }
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}
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void Board::Pic::mask(unsigned const i)
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void Board::Bcm2835_pic::mask(unsigned const i)
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{
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if (i < 32) { write<Irq_disable_gpu_1>(1 << i); }
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else { write<Irq_disable_gpu_2>(1 << (i - 32)); }
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}
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void Board::Pic::irq_mode(unsigned, unsigned, unsigned) { }
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void Board::Bcm2835_pic::irq_mode(unsigned, unsigned, unsigned) { }
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@ -20,7 +20,7 @@
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namespace Board {
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class Global_interrupt_controller;
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class Pic;
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class Bcm2835_pic;
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}
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@ -38,7 +38,7 @@ class Board::Global_interrupt_controller
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};
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class Board::Pic : Genode::Mmio
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class Board::Bcm2835_pic : Genode::Mmio
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{
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public:
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@ -128,7 +128,8 @@ class Board::Pic : Genode::Mmio
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public:
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Pic(Global_interrupt_controller &global_irq_ctrl);
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Bcm2835_pic(Global_interrupt_controller &global_irq_ctrl,
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Genode::addr_t irq_ctrl_base = 0);
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bool take_request(unsigned &irq);
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void finish_request() { }
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@ -16,13 +16,14 @@
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#include <platform.h>
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Board::Pic::Pic(Global_interrupt_controller &)
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Board::Bcm2837_pic::Bcm2837_pic(Global_interrupt_controller &global_irq_ctrl)
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:
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Genode::Mmio(Genode::Platform::mmio_to_virt(Board::LOCAL_IRQ_CONTROLLER_BASE))
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Genode::Mmio(Genode::Platform::mmio_to_virt(Board::LOCAL_IRQ_CONTROLLER_BASE)),
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_bcm2835_pic(global_irq_ctrl, Board::IRQ_CONTROLLER_BASE)
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{ }
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bool Board::Pic::take_request(unsigned & irq)
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bool Board::Bcm2837_pic::take_request(unsigned & irq)
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{
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unsigned cpu = Genode::Cpu::executing_id();
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Core_irq_source<0>::access_t src = 0;
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@ -49,11 +50,17 @@ bool Board::Pic::take_request(unsigned & irq)
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return true;
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}
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// Gpu interrupt
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if (cpu == 0 && Core_irq_source<0>::Gpu::get(src)) {
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auto result = _bcm2835_pic.take_request(irq);
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return result;
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}
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return false;
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}
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void Board::Pic::_timer_irq(unsigned cpu, bool enable)
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void Board::Bcm2837_pic::_timer_irq(unsigned cpu, bool enable)
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{
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unsigned v = enable ? 1 : 0;
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switch (cpu) {
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@ -74,7 +81,7 @@ void Board::Pic::_timer_irq(unsigned cpu, bool enable)
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}
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void Board::Pic::_ipi(unsigned cpu, bool enable)
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void Board::Bcm2837_pic::_ipi(unsigned cpu, bool enable)
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{
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unsigned v = enable ? 1 : 0;
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switch (cpu) {
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@ -95,33 +102,31 @@ void Board::Pic::_ipi(unsigned cpu, bool enable)
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}
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void Board::Pic::unmask(unsigned const i, unsigned cpu)
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void Board::Bcm2837_pic::unmask(unsigned const i, unsigned cpu)
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{
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switch (i) {
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case TIMER_IRQ: _timer_irq(cpu, true); return;
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case IPI: _ipi(cpu, true); return;
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}
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Genode::raw("irq of peripherals != timer not implemented yet! (irq=", i, ")");
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if (cpu == 0) _bcm2835_pic.unmask(i, cpu);
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}
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void Board::Pic::mask(unsigned const i)
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void Board::Bcm2837_pic::mask(unsigned const i)
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{
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unsigned cpu = Genode::Cpu::executing_id();
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switch (i) {
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case TIMER_IRQ: _timer_irq(cpu, false); return;
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case IPI: _ipi(cpu, false); return;
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}
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Genode::raw("irq of peripherals != timer not implemented yet! (irq=", i, ")");
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if (cpu == 0) _bcm2835_pic.mask(i);
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}
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void Board::Pic::irq_mode(unsigned, unsigned, unsigned) { }
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void Board::Bcm2837_pic::irq_mode(unsigned, unsigned, unsigned) { }
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void Board::Pic::send_ipi(unsigned cpu_target)
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void Board::Bcm2837_pic::send_ipi(unsigned cpu_target)
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{
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switch (cpu_target) {
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case 0: write<Core_mailbox_set<0>>(1); return;
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@ -16,14 +16,16 @@
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#include <util/mmio.h>
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#include <spec/arm/bcm2835_pic.h>
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namespace Board {
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class Global_interrupt_controller { };
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class Pic;
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/* Global_interrupt_controller from Bcm2835_pic */
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class Bcm2837_pic;
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}
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class Board::Pic : Genode::Mmio
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class Board::Bcm2837_pic : Genode::Mmio
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{
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public:
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@ -45,7 +47,20 @@ class Board::Pic : Genode::Mmio
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struct Core_mailbox_irq_control : Register<0x50+CPU_NUM*0x4, 32> {};
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template <unsigned CPU_NUM>
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struct Core_irq_source : Register<0x60+CPU_NUM*0x4, 32> {};
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struct Core_irq_source : Register<0x60+CPU_NUM*0x4, 32> {
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struct CntPsIrq : Register<0x60+CPU_NUM*0x4, 32>::template Bitfield<0, 1> { };
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struct CntPnIrq : Register<0x60+CPU_NUM*0x4, 32>::template Bitfield<1, 1> { };
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struct CntHpIrq : Register<0x60+CPU_NUM*0x4, 32>::template Bitfield<2, 1> { };
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struct CntVIrq : Register<0x60+CPU_NUM*0x4, 32>::template Bitfield<3, 1> { };
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struct MBox0 : Register<0x60+CPU_NUM*0x4, 32>::template Bitfield<4, 1> { };
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struct MBox1 : Register<0x60+CPU_NUM*0x4, 32>::template Bitfield<5, 1> { };
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struct MBox2 : Register<0x60+CPU_NUM*0x4, 32>::template Bitfield<6, 1> { };
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struct MBox3 : Register<0x60+CPU_NUM*0x4, 32>::template Bitfield<7, 1> { };
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struct Gpu : Register<0x60+CPU_NUM*0x4, 32>::template Bitfield<8, 1> { };
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struct Pmu : Register<0x60+CPU_NUM*0x4, 32>::template Bitfield<9, 1> { };
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struct Axi : Register<0x60+CPU_NUM*0x4, 32>::template Bitfield<10, 1> { };
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struct Timer : Register<0x60+CPU_NUM*0x4, 32>::template Bitfield<11, 1> { };
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};
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template <unsigned CPU_NUM>
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struct Core_mailbox_set : Register<0x80+CPU_NUM*0x10, 32> {};
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@ -56,9 +71,11 @@ class Board::Pic : Genode::Mmio
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void _ipi(unsigned cpu, bool enable);
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void _timer_irq(unsigned cpu, bool enable);
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Bcm2835_pic _bcm2835_pic;
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public:
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Pic(Global_interrupt_controller &);
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Bcm2837_pic(Global_interrupt_controller &);
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bool take_request(unsigned &irq);
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void finish_request() { }
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@ -29,11 +29,17 @@ namespace Hw::Rpi3_board {
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UART_SIZE = 0x1000,
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UART_CLOCK = 250000000,
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IRQ_CONTROLLER_BASE = 0x3f00b000,
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IRQ_CONTROLLER_BASE = 0x3f00b200,
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IRQ_CONTROLLER_SIZE = 0x1000,
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LOCAL_IRQ_CONTROLLER_BASE = 0x40000000,
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LOCAL_IRQ_CONTROLLER_SIZE = 0x1000,
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USB_DWC_OTG_BASE = 0x3f980000,
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USB_DWC_OTG_SIZE = 0x20000,
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/* USB host controller */
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DWC_IRQ = 9,
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};
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};
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61
repos/base/include/drivers/platform/bcm2837_control.h
Normal file
61
repos/base/include/drivers/platform/bcm2837_control.h
Normal file
@ -0,0 +1,61 @@
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/*
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* \brief Driver for the platform specific functionality for bcm2837
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* \author Tomasz Gajewski
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* \date 2019-12-28
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*/
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/*
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* Copyright (C) 2011-2019 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _INCLUDE__DRIVERS__PLATFORM__BCM2837_CONTROL_H_
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#define _INCLUDE__DRIVERS__PLATFORM__BCM2837_CONTROL_H_
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/* Genode includes */
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#include <util/mmio.h>
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namespace Genode { class Bcm2837_control; }
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class Genode::Bcm2837_control : Mmio
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{
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public:
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struct ControlRegister : public Register<0x0, 32>
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{
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struct CoreTimeClockSource : Bitfield<8,1> { };
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struct TimerIncrement : Bitfield<9,1> { };
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};
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struct CoreTimerPrescaler : public Register<0x8, 32>
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{
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};
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inline Bcm2837_control(addr_t const base);
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inline void initialize_timer_frequency();
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};
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Genode::Bcm2837_control::Bcm2837_control(addr_t const base)
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:
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Mmio(base)
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{ }
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void Genode::Bcm2837_control::initialize_timer_frequency()
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{
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/*
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* Set prescaler value to achieve divider value equal to 1.
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* Value taken from chapter "3.1.1 Timer clock" from QA7_rev3.4.pdf
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* document describing the BCM2836 chip.
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*/
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write<CoreTimerPrescaler>(0x80000000);
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}
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#endif /* _INCLUDE__DRIVERS__PLATFORM__BCM2837_CONTROL_H_ */
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