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73eb7a8d4b
Instead of mapping all physical memory 1:1 into core/kernel's address space, this commit limits the 1:1 mapping to the binary image, and I/O memory regions used by the kernel only. All subsequent memory accesses of core are done by mapping the corresponding memory on demand, and not necessarily 1:1. This commit has several side effects: The page table code had to be revisited completely. The kernel inserts no longer anything into the page tables, apart from the initial translations to have the core/kernel image available when enabling the MMU. The page tables and higher level translation tables are no longer named Tlb, but Translation_table instead. There is no indirection class required to define the translation tables of a concrete SoC, the appropriated ARM specifier is sufficient. The ability to map core's memory the same way like it's done for all other protection domains, makes a special treatment of core's threads (no context area) obsolete. Ref #567 (partly solves it) Fix #723 Fix #1068 |
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| .. | ||
| arm/kernel | ||
| base | ||
| cpu_session | ||
| exynos5_uart/drivers | ||
| irq_session | ||
| kernel | ||
| pl011/drivers | ||
| platform | ||
| signal_session | ||
| tl16c750/drivers | ||
| vm_session | ||