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- Enable the "platform-level interrupt controller" PLIC on base-hw - The RISC-V specification offers only a register description, but no layout for the register set. This implies the layout is platform dependent, and therefore, implemented separately for Qemu issue #4042 |
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arm | ||
arm_64 | ||
arm_v6 | ||
arm_v7 | ||
arm_v8 | ||
cortex_a8 | ||
cortex_a9 | ||
cortex_a15 | ||
riscv | ||
x86_64 |