Martin Stein 1336b0a751 mmio: upper-bounds checks ... The classes Genode::Mmio, Genode::Register_set, Genode::Attached_mmio, and Platform::Device::Mmio now receive a template parameter 'size_t SIZE'. In each type that derives from one of these classes, it is now statically checked that the range of each Genode::Register::Register- and Genode::Register_set::Register_array-deriving sub-type is within [0..SIZE). That said, SIZE is the minimum size of the memory region provided to the above mentioned Mmio classes in order to avoid page faults or memory corruption when accessing the registers and register arrays declared inside. Note, that the range end of a register array is not the end of the last item but the end of integer access that is used for accessing the last bit in the last item. The constructors of Genode::Mmio, Genode::Attached_mmio, and Platform::Device::Mmio now receive an argument 'Byte_range_ptr range' that is expected to be the range of the backing memory region. In each type that derives from on of these classes, it is now dynamically checked that 'range.num_bytes >= SIZE', thereby implementing the above mention protection against page faults and memory corruption. The rest of the commit adapts the code throughout the Genode Labs repositories regarding the changes. Note that for that code inside Core, the commits mostly uses a simplified approach by constructing MMIO objects with range [base..base+SIZE) and not with a mapping- or specification-related range size. This should be fixed in the future. Furthermore, there are types that derive from an MMIO class but don't declare any registers or register arrays (especially with Platform::Device::Mmio). In this case SIZE is set to 0. This way, the parameters must be actively corrected by someone who later wants to add registers or register arrays, plus the places can be easily found by grep'ing for Mmio<0>. Fix #4081		2024-02-26 08:59:07 +01:00
..
32bit/base	Adjust file headers to refer to the AGPLv3	2017-02-28 12:59:29 +01:00
64bit/base	Adjust file headers to refer to the AGPLv3	2017-02-28 12:59:29 +01:00
arm/cpu	memcpy (arm): cache align and use pld for speedup	2022-04-13 08:08:01 +02:00
arm_64	hw: fix vmm_arm test on arm_v8a	2023-10-04 13:22:08 +02:00
arm_v6	Move timer from os to base repository	2019-01-14 12:33:57 +01:00
arm_v7	Move timer from os to base repository	2019-01-14 12:33:57 +01:00
riscv	base: provide generic cpu/string.h	2023-01-24 12:07:28 +01:00
x86	mmio: upper-bounds checks	2024-02-26 08:59:07 +01:00
x86_32	nova: add guarded access to MSRs	2023-10-25 08:58:52 +02:00
x86_64	nova: add guarded access to MSRs	2023-10-25 08:58:52 +02:00