Commit Graph

793 Commits

Author SHA1 Message Date
7feea78991 timeout: rework timeout framework
* get rid of alarm abstraction
* get rid of Timeout::Time type
* get rid of pointer arguments
* get rid of _discard_timeout indirection
* get rid of 65th bit in stored time values
* get rid of Timeout_scheduler interface
* get rid of uninitialized deadlines
* get rid of default arguments
* get rid of Timeout::_periodic
* get rid of Timeout::Raw
* use list abstraction
* only one interface for timeout handlers
* rework locking scheme to be smp safe
* move all method definitions to CC file
* name mutexes more accurate
* fix when & how to set time-source timeout
* fix deadlocks

Fixes #3884
2020-10-09 13:35:56 +02:00
90bea1499e core: store new affinity on successful migration
Adjust the base-* platforms to acknowledge new thread location solely if
migration is supported and succeeded. Otherwise the wrong thread
locations are observed via the trace session and utilization time calculation
get wrong.

Issue #3842
2020-10-09 13:33:36 +02:00
5f5ad41ad3 hw: unify irq enumeration for Raspberri Pi
By now, the enumeration of peripheral interrupts on Raspberry Pi 1 was
different in between base-hw kernel and Fiasco.OC. Therefore, hacks were
needed in every driver to request the correct interrupt number dependent
on the kernel. Before reproducing the same in the platform driver for rpi,
we can more easily use the same enumeration with base-hw.

Ref #3864
2020-08-25 11:50:12 +02:00
70f98fcc44 hw: implement Pd_session::managing_system for ATF
To access the ARM Trusted Firmware from the platform driver
fill the new `managing_system` call of the PD session with life resp.
do a SMC call on behalf of the client.

Fix #3816
2020-08-25 11:50:11 +02:00
fd682cd470 hw: check descriptor validity in LPAE lookup
Fixes #3828
2020-07-30 08:49:23 +02:00
41380ff769 base: remove Cancelable_lock
- base/cancelable_lock.h becomes base/lock.h
- all members become private within base/lock.h
- solely Mutex and Blockade are friends to use base/lock.h

Fixes #3819
2020-07-30 08:49:23 +02:00
f3efbe50bb base: remove deprecated cancel_blocking() support
for threads.

Fixes #3806
2020-07-13 11:33:12 +02:00
1f91fd3f7d hw: scale imx8q_evk cpu to 1.5 GHz 2020-06-29 14:25:27 +02:00
04d8c859d8 hw: enable branch predictor on rpi
* Z-bit was never enabled for rpi1
* Write buffer, and TCM bits are deprecated in this processor generation
  so do not use them

Ref #3247
2020-06-22 09:39:40 +02:00
b134867f31 Remove Rpc_entrypoint::Native_context
This patch largely reverts the commit "base: lay groundwork for
base-linux caps change" because the use of 'epoll' instead of 'select'
alleviated the need to allocate large FD sets, which motivated the
introduction of the 'Native_context' hook.

Related to issue #3581
2020-04-21 16:50:37 +02:00
0e49336b96 Retire Exynos 5 support (fix #3725) 2020-04-17 12:53:57 +02:00
941e918b46 vmm: unify armv7/v8 virtualization
Fix #3638
2020-04-17 12:52:02 +02:00
74e75d7fbc hw: enable virtualization support for virt_qemu
Ref #3638
2020-04-17 12:51:53 +02:00
58db6542f8 hw: check for security extension support in GICv2
Ref #3638
2020-04-17 12:51:44 +02:00
ff378a8c5b hw: cache maintainance on mapping removal too
Older ARM processors like ARMv6, or Cortex A8 need to write back changes
of the page-tables to physical ram because the MMU does not use the cache.
This naturally needs to be done not only when adding a mapping,
but on removal too.

Fix #3715
2020-04-17 12:40:13 +02:00
3956530634 base: use Mutex/Blockade
Issue #3612
2020-04-17 12:40:12 +02:00
e87d60ddf7 core: use Mutex/Blockade
Issue #3612
2020-04-17 12:40:12 +02:00
f051065582 Retire OMAP4 support
Fix #2850
2020-04-17 12:39:32 +02:00
585c4b8c69 hw: Add support for Qemu virt arm platforms.
This patch adds support for booting base-hw kernel on qemu-arm virt
machines. The arm_virt machine has 2GB of RAM, 2 Cortex A15 cores and
uses GICv2 interrupt controller. The arm_64_virt machine also has 2GB of
RAM, but has 4 Cortex A53 cores and uses GICv3. Both machines use PSCI
to boot additional CPU cores.

Fixes #3673
2020-04-17 12:39:32 +02:00
dad1de1865 hw: Add interface for making basic ARM PSCI calls.
So far this only exposes two functions allowing the code to turn on
additional CPUs. There is much more functionality defined by PSCI spec
but so far its not needed by Genode.

Fixes #3672
2020-04-17 12:39:32 +02:00
256b2fa3e1 hw: cortex a9 diagnostic register fixup
This is a follow-up fix for commit 202333c881.
It checks for the diagnostic registers being already setup correctly.
Otherwise on platforms with secure firmware, like Pandaboard it will stuck.

Ref #3639
2020-03-26 11:39:02 +01:00
0f3ac4cb9f base-hw: let upgrade_cap_slab reflect Out_of_caps
This patch reflects the Out_of_caps exception from core to the client,
in addition to the already covered Out_of_ram exception. It thereby
eliminates a potential abort in core, which I observed with the
tool_chain_auto.run script:

  Kernel: RPC upgrade_cap_slab
  Error: Uncaught exception of type 'Genode::Quota_guard<Genode::Cap_quota>::Limit_exceeded'
  Warning: abort called - thread: entrypoint

In addition to propagating the exception, the patch add the client-side
exception-handling code to the base library.

Fixes #3703
2020-03-26 11:38:59 +01:00
6d48b5484d hw: correct the ARM cache maintainance operations
This commit fixes the following issues regarding cache maintainance
under ARM:

* read out I-, and D-cache line size at runtime and use the correct one
* remove 'update_data_region' call from unprivileged syscalls
* rename 'update_instr_region' syscall to 'cache_coherent_region' to
  reflect what it doing, namely make I-, and D-cache coherent
* restrict 'cache_coherent_region' syscall to one page at a time
* lookup the region given in a 'cache_coherent_region' syscall in the
  page-table of the PD to prevent machine exceptions in the kernel
* only clean D-cache lines, do not invalidate them when pages where
  added on Cortex-A8 and ARMv6 (MMU sees phys. memory here)
* remove unused code relicts of cache maintainance

In addition it introduces per architecture memory clearance functions
used by core, when preparing new dataspaces. Thereby, it optimizes:

* on ARMv7 using per-word assignments
* on ARMv8 using cacheline zeroing
* on x86_64 using 'rept stosq' assembler instruction

Fix #3685
2020-03-26 11:38:55 +01:00
e096202b1f hw/x86: use PAT for write combining support
Fixes #3623
2020-03-26 11:38:54 +01:00
44ace04b95 hw/x86: add cpuid register macro
Issue #3623
2020-03-26 11:38:54 +01:00
507a34b3d0 hw/x86: implement wrmsr in macro
Issue #3623
2020-03-26 11:38:54 +01:00
a7a9855493 base: lay groundwork for base-linux caps change
Include the necessary hooks to introduce file descriptor
based capabilities in base linux.

Issue #3581
2020-02-27 14:46:58 +01:00
8cc48d5688 hw: be more accurate in synchronizing ASID/Pages
Fix #3651
2020-02-20 12:11:23 +01:00
5440cd4b50 base: use blockade in thread
Issue #3612
2020-02-20 12:11:22 +01:00
00f69bc70d base: add mutex as derivate of lock
The mutex class is more restrictive in usage compared to
Genode::Lock.

- At initialiation time it is ever unlocked.
- No thread is permitted to lock twice. Warn about it
  in case it happens.
- Only the lock onwer is permitted to unlock the mutex.
  Warn about it and don't unlock the mutex in case it happens.

Issue #3612
2020-02-20 12:11:22 +01:00
725d16e18e hw: optimize ipc capability allocation
In preparation of ipc receive, by now a bunch of capabilities got
allocated to be ready iin case of capability receiption. After that
unuse slots were freed again. This overhead of senseless (de-)allocations
is replaced in this commit by just restock capability slots that got
used by the last receive.

Fix #3640
2020-02-20 12:11:22 +01:00
e42a205a51 base-hw: Ada-compliant scheduler method signatures
Ref #3308
2020-02-20 12:11:22 +01:00
0d5f185267 base-hw: no pointers in scheduler interface
Ref #3308
2020-02-20 12:11:22 +01:00
c146a215fb base-hw: cpu scheduler without inheritance
Ref #3308
2020-02-20 12:11:21 +01:00
eef7b5e168 base-hw: double list without inheritance
Ref #3308
2020-02-20 12:11:21 +01:00
793e12f8f3 base-hw: no error return codes in signaling
Error return codes are used with non-const functions in the signaling modules.
This would have been impractical for the in-place translation of the module to
Ada in the context of the Spunky project. Besides, it is easy to get rid of
them and it makes the execution flow more clear.

Ref #3308
2020-02-20 12:11:21 +01:00
751e6430fa base-hw: obsolete Kernel::Thread::_signal_receiver
Ref #3308
2020-02-20 12:11:21 +01:00
9eb20c2be7 base-hw: no pointer arguments in signaling
Besides reducing the use of pointers in base-hw, this prepares for the in-place
translation of the signaling module to Ada in the context of the Spunky
project.

Ref #3308
2020-02-20 12:11:21 +01:00
5e460394d2 base-hw: do not inherit Kernel::Object
This prevents the use of Kernel::Object as base class for the specific kernel
objects and instead makes it a member of the kernel objects. Besides
simplifying inheritance hierarchies in base-hw, this prepares for the in-place
translation of the signaling module (and others) to Ada in the context of the
Spunky project.

Ref #3308
2020-02-20 12:11:21 +01:00
88043e144a base-hw: no virtual functions in signaling
Besides simplifying the execution flow in the signaling module, this prepares
for the in-place translation of the signaling module to Ada in the context of
the Spunky project.

Ref #3308
2020-02-20 12:11:21 +01:00
3cc7774fe4 base-hw: Ada/SPARK-friendly Ipc_node interface
This prevents the use of C++ features in the public method interface of the
synchronous-IPC module that would be impractical for the in-place
translation of the module into Ada in the context of the Spunky project.

* Get rid of thread accessor.
* Get rid of non-const functions with return values.
* Get rid of pointer return-values.

Ref #3308
2020-02-20 12:11:21 +01:00
a04243aaf4 base-hw: remove unused Ipc_node accessor methods
Ref #3308
2020-02-20 12:11:21 +01:00
5a95183c3e base-hw: avoid that Ipc_node inherits
Besides simplifying inheritance hierarchies in base-hw, this prepares for the
in-place translation of the synchronous-IPC module to Ada in the context of the
Spunky project.

Ref #3308
2020-02-20 12:11:21 +01:00
6a5aa18a7b base-hw: no PD code / virt methods in Ipc_node
This is a simplication of the asyncronous-IPC module of the base-hw kernel.
Besides structuring the code in a cleaner way, it prepares for the in-place
translation of the module into Ada in the context of the Spunky project.

* Get rid of virtual methods in Ipc_node.
* Move all stuff related to protection domains, capabilities, and UTCBs to
  the Thread class. this code might later be moved to a dedicated module, but
  for now it's just fine to have it done by the thread module.

Ref #3308
2020-02-20 12:11:21 +01:00
79fba6c2ac core: add kernel-specific UTCB quota bookkeeping
Fix #859
2020-02-20 12:11:21 +01:00
4f217b19a9 hw: add CPU wake up code for rpi3
Moved code waking up processors for Cortex A53 before changing privilege
level because sending events to higher privilege levels is not allowed.

Fixed enable_mmu for Cortex A53 to properly return cpu id.

Fixed starting code for secondary cores to properly initialize stacks.

Added code to wake up secondary cores on rpi3.

Ref #3573
2020-02-20 12:08:17 +01:00
202333c881 hw: cortex a9 diagnostic register initialization
We cannot count on the correct initialization of the diagnostic register
of the secondary cores. But the boot core gets initialized by the bootchain,
so we can copy over those values.

Fix #3639
2020-02-20 12:08:17 +01:00
56ef7ca9e7 hw: enable ARMv8 performance counter
Fix #3618
2020-02-04 16:05:01 +01:00
7b964fa700 base: add affinity space info to platform info
Issue #3599
2020-02-04 15:51:10 +01:00
1902d1a06b hw: do not map boot modules in bootstrap
This commit safes virtual address space.
2020-02-04 15:51:08 +01:00