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hw: rename <spec>::Cpu in <spec>::Processor_driver

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ref #1083
This commit is contained in:
Martin Stein 2014-03-03 00:12:53 +01:00 committed by Norman Feske
parent 5d444a12dc
commit effeb765b9
16 changed files with 43 additions and 43 deletions
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2
base-hw/src/core/arndale/processor_driver.h
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@ -22,7 +22,7 @@ namespace Genode
/**
* CPU driver for core
*/
class Processor_driver : public Cortex_a15::Cpu
class Processor_driver : public Cortex_a15::Processor_driver
{
public:

2
base-hw/src/core/imx31/processor_driver.h
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@ -22,7 +22,7 @@ namespace Genode
/**
* CPU driver for core
*/
class Processor_driver : public Arm_v6::Cpu { };
class Processor_driver : public Arm_v6::Processor_driver { };
}
namespace Kernel { typedef Genode::Processor_driver Processor_driver; }

2
base-hw/src/core/imx53/processor_driver.h
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@ -22,7 +22,7 @@ namespace Genode
/**
* CPU driver for core
*/
class Processor_driver : public Cortex_a8::Cpu
class Processor_driver : public Cortex_a8::Processor_driver
{
public:

2
base-hw/src/core/odroid_xu/processor_driver.h
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@ -22,7 +22,7 @@ namespace Genode
/**
* CPU driver for core
*/
class Processor_driver : public Cortex_a15::Cpu
class Processor_driver : public Cortex_a15::Processor_driver
{
public:

2
base-hw/src/core/panda/processor_driver.h
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@ -22,7 +22,7 @@ namespace Genode
/**
* CPU driver for core
*/
class Processor_driver : public Cortex_a9::Cpu
class Processor_driver : public Cortex_a9::Processor_driver
{
public:

2
base-hw/src/core/pbxa9/processor_driver.h
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@ -22,7 +22,7 @@ namespace Genode
/**
* CPU driver for core
*/
class Processor_driver : public Cortex_a9::Cpu
class Processor_driver : public Cortex_a9::Processor_driver
{
public:

2
base-hw/src/core/processor_driver/arm.h
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@ -29,7 +29,7 @@ namespace Arm
/**
* CPU driver for core
*/
struct Cpu
struct Processor_driver
{
enum {
TTBCR_N = 0,

22
base-hw/src/core/processor_driver/arm_v6.h
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@ -29,12 +29,12 @@ namespace Arm_v6
/**
* CPU driver for core
*/
struct Cpu : Arm::Cpu
struct Processor_driver : Arm::Processor_driver
{
/**
* Cache type register
*/
struct Ctr : Arm::Cpu::Ctr
struct Ctr : Arm::Processor_driver::Ctr
{
struct P : Bitfield<23, 1> { }; /* page mapping restriction on */
};
@ -42,7 +42,7 @@ namespace Arm_v6
/**
* System control register
*/
struct Sctlr : Arm::Cpu::Sctlr
struct Sctlr : Arm::Processor_driver::Sctlr
{
struct W : Bitfield<3,1> { }; /* enable write buffer */
@ -75,7 +75,7 @@ namespace Arm_v6
static access_t init_virt_kernel()
{
return base_value() |
Arm::Cpu::Sctlr::init_virt_kernel() |
Arm::Processor_driver::Sctlr::init_virt_kernel() |
W::bits(0) |
B::bits(B::LITTLE) |
S::bits(0) |
@ -93,7 +93,7 @@ namespace Arm_v6
static access_t init_phys_kernel()
{
return base_value() |
Arm::Cpu::Sctlr::init_phys_kernel() |
Arm::Processor_driver::Sctlr::init_phys_kernel() |
W::bits(0) |
B::bits(B::LITTLE) |
S::bits(0) |
@ -109,7 +109,7 @@ namespace Arm_v6
/**
* Translation table base control register 0
*/
struct Ttbr0 : Arm::Cpu::Ttbr0
struct Ttbr0 : Arm::Processor_driver::Ttbr0
{
struct C : Bitfield<0,1> /* inner cachable mode */
{
@ -125,7 +125,7 @@ namespace Arm_v6
*/
static access_t init_virt_kernel(addr_t const sect_table)
{
return Arm::Cpu::Ttbr0::init_virt_kernel(sect_table) |
return Arm::Processor_driver::Ttbr0::init_virt_kernel(sect_table) |
P::bits(0) |
C::bits(C::NON_CACHEABLE);
}
@ -217,11 +217,11 @@ namespace Arm_v6
}
/**************
** Arm::Cpu **
**************/
/***************************
** Arm::Processor_driver **
***************************/
void Arm::Cpu::flush_data_caches()
void Arm::Processor_driver::flush_data_caches()
{
asm volatile ("mcr p15, 0, %[rd], c7, c14, 0" :: [rd]"r"(0) : );
}

28
base-hw/src/core/processor_driver/arm_v7.h
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@ -25,7 +25,7 @@ namespace Arm_v7
/**
* CPU driver for core
*/
struct Cpu : Arm::Cpu
struct Processor_driver : Arm::Processor_driver
{
/**
* Secure configuration register
@ -61,7 +61,7 @@ namespace Arm_v7
/**
* System control register
*/
struct Sctlr : Arm::Cpu::Sctlr
struct Sctlr : Arm::Processor_driver::Sctlr
{
struct Unused_0 : Bitfield<3,4> { }; /* shall be ~0 */
struct Sw : Bitfield<10,1> { }; /* support SWP and SWPB */
@ -96,7 +96,7 @@ namespace Arm_v7
static access_t init_phys_kernel()
{
return base_value() |
Arm::Cpu::Sctlr::init_phys_kernel() |
Arm::Processor_driver::Sctlr::init_phys_kernel() |
Sw::bits(0) |
Ha::bits(0) |
Nmfi::bits(0) |
@ -109,7 +109,7 @@ namespace Arm_v7
static access_t init_virt_kernel()
{
return base_value() |
Arm::Cpu::Sctlr::init_virt_kernel() |
Arm::Processor_driver::Sctlr::init_virt_kernel() |
Sw::bits(0) |
Ha::bits(0) |
Nmfi::bits(0) |
@ -120,7 +120,7 @@ namespace Arm_v7
/**
* Translation table base register 0
*/
struct Ttbr0 : Arm::Cpu::Ttbr0
struct Ttbr0 : Arm::Processor_driver::Ttbr0
{
struct Nos : Bitfield<5,1> { }; /* not outer shareable */
@ -134,7 +134,7 @@ namespace Arm_v7
*/
static access_t init_virt_kernel(addr_t const sect_table)
{
return Arm::Cpu::Ttbr0::init_virt_kernel(sect_table) |
return Arm::Processor_driver::Ttbr0::init_virt_kernel(sect_table) |
Nos::bits(0) |
Irgn_1::bits(0) |
Irgn_0::bits(1);
@ -144,7 +144,7 @@ namespace Arm_v7
/**
* Translation table base control register
*/
struct Ttbcr : Arm::Cpu::Ttbcr
struct Ttbcr : Arm::Processor_driver::Ttbcr
{
struct Pd0 : Bitfield<4,1> { }; /* disable walk for TTBR0 */
struct Pd1 : Bitfield<5,1> { }; /* disable walk for TTBR1 */
@ -154,7 +154,7 @@ namespace Arm_v7
*/
static access_t init_virt_kernel()
{
return Arm::Cpu::Ttbcr::init_virt_kernel() |
return Arm::Processor_driver::Ttbcr::init_virt_kernel() |
Pd0::bits(0) |
Pd1::bits(0);
}
@ -194,7 +194,7 @@ namespace Arm_v7
static bool secure_mode()
{
if (!Board::SECURITY_EXTENSION) return 0;
return !Cpu::Scr::Ns::get(Cpu::Scr::read());
return !Scr::Ns::get(Scr::read());
}
@ -258,11 +258,11 @@ namespace Arm_v7
}
/**************
** Arm::Cpu **
**************/
/***************************
** Arm::Processor_driver **
***************************/
void Arm::Cpu::flush_data_caches()
void Arm::Processor_driver::flush_data_caches()
{
/*
* FIXME This routine is taken from the ARMv7 reference manual by
@ -318,7 +318,7 @@ void Arm::Cpu::flush_data_caches()
}
Arm::Cpu::Psr::access_t Arm::Cpu::Psr::init_user_with_trustzone()
Arm::Processor_driver::Psr::access_t Arm::Processor_driver::Psr::init_user_with_trustzone()
{
return M::bits(M::USER) |
T::bits(T::ARM) |

2
base-hw/src/core/processor_driver/cortex_a15.h
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@ -29,7 +29,7 @@ namespace Cortex_a15
/**
* CPU driver for core
*/
struct Cpu : Arm_v7::Cpu
struct Processor_driver : Arm_v7::Processor_driver
{
/**
* Ensure that TLB insertions get applied

2
base-hw/src/core/processor_driver/cortex_a8.h
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@ -24,7 +24,7 @@ namespace Cortex_a8
/**
* CPU driver for core
*/
struct Cpu : Arm_v7::Cpu
struct Processor_driver : Arm_v7::Processor_driver
{
/**
* Ensure that TLB insertions get applied

2
base-hw/src/core/processor_driver/cortex_a9.h
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@ -25,7 +25,7 @@ namespace Cortex_a9
/**
* CPU driver for core
*/
struct Cpu : Arm_v7::Cpu
struct Processor_driver : Arm_v7::Processor_driver
{
enum
{

2
base-hw/src/core/rpi/processor_driver.h
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@ -17,7 +17,7 @@
/* core includes */
#include <processor_driver/arm_v6.h>
namespace Genode { class Processor_driver : public Arm_v6::Cpu { }; }
namespace Genode { class Processor_driver : public Arm_v6::Processor_driver { }; }
namespace Kernel { typedef Genode::Processor_driver Processor_driver; }

8
base-hw/src/core/timer/cortex_a9.h
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@ -18,7 +18,7 @@
#include <util/mmio.h>
/* core includes */
#include <processor_driver/cortex_a9.h>
#include <processor_driver.h>
namespace Cortex_a9
{
@ -27,7 +27,7 @@ namespace Cortex_a9
*/
class Timer : public Mmio
{
enum { TICS_PER_MS = Cortex_a9::Cpu::PRIVATE_TIMER_CLK / 1000, };
enum { TICS_PER_MS = Processor_driver::PRIVATE_TIMER_CLK / 1000, };
/**
* Load value register
@ -58,7 +58,7 @@ namespace Cortex_a9
/**
* Constructor, clears the interrupt output
*/
Timer() : Mmio(Cortex_a9::Cpu::PRIVATE_TIMER_MMIO_BASE)
Timer() : Mmio(Processor_driver::PRIVATE_TIMER_MMIO_BASE)
{
write<Control::Timer_enable>(0);
_clear_interrupt();
@ -69,7 +69,7 @@ namespace Cortex_a9
*/
static unsigned interrupt_id(unsigned)
{
return Cortex_a9::Cpu::PRIVATE_TIMER_IRQ;
return Processor_driver::PRIVATE_TIMER_IRQ;
}
/**

4
base-hw/src/core/tlb/arm_v7.h
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@ -16,7 +16,7 @@
/* core includes */
#include <tlb/arm.h>
#include <processor_driver/arm_v7.h>
#include <processor_driver.h>
namespace Arm_v7
{
@ -82,7 +82,7 @@ class Arm_v7::Section_table : public Arm::Section_table
/**
* Constructor
*/
Section_table() : _secure(Arm_v7::Cpu::secure_mode()) { }
Section_table() : _secure(Processor_driver::secure_mode()) { }
/**
* Insert one atomic translation into this table

2
base-hw/src/core/vea9x4/processor_driver.h
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@ -22,7 +22,7 @@ namespace Genode
/**
* CPU driver for core
*/
class Processor_driver : public Cortex_a9::Cpu
class Processor_driver : public Cortex_a9::Processor_driver
{
public: