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base-hw: unprivileged cache maintenance on ARMv8

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Set 'Sctlr_el1::Uci' bit to allow for executing cache clean and
invalidate instruction from user space.

Issue #4339.
This commit is contained in:
Josef Söntgen 2021-12-08 17:15:06 +01:00 committed by Christian Helmuth
parent 8fe7fa5532
commit e8f748cfed
2 changed files with 2 additions and 0 deletions
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1
repos/base-hw/src/bootstrap/spec/arm_64/cortex_a53_mmu.cc
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@ -199,6 +199,7 @@ unsigned Bootstrap::Platform::enable_mmu()
Cpu::Sctlr::Sa0::set(sctlr, 1);
Cpu::Sctlr::Sa::set(sctlr, 0);
Cpu::Sctlr::Uct::set(sctlr, 1);
Cpu::Sctlr::Uci::set(sctlr, 1);
Cpu::Sctlr_el1::write(sctlr);
return cpu_id;

1
repos/base-hw/src/include/hw/spec/arm_64/cpu.h
View File

@ -168,6 +168,7 @@ struct Hw::Arm_64_cpu
struct I : Bitfield<12, 1> { };
struct Uct : Bitfield<15, 1> { };
struct Wxn : Bitfield<19, 1> { };
struct Uci : Bitfield<26, 1> { };
};
SYSTEM_REGISTER(64, Sctlr_el1, sctlr_el1);