From e8f748cfed5901bc0deb00cba54db8bfd864dad6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Josef=20S=C3=B6ntgen?= Date: Wed, 8 Dec 2021 17:15:06 +0100 Subject: [PATCH] base-hw: unprivileged cache maintenance on ARMv8 Set 'Sctlr_el1::Uci' bit to allow for executing cache clean and invalidate instruction from user space. Issue #4339. --- repos/base-hw/src/bootstrap/spec/arm_64/cortex_a53_mmu.cc | 1 + repos/base-hw/src/include/hw/spec/arm_64/cpu.h | 1 + 2 files changed, 2 insertions(+) diff --git a/repos/base-hw/src/bootstrap/spec/arm_64/cortex_a53_mmu.cc b/repos/base-hw/src/bootstrap/spec/arm_64/cortex_a53_mmu.cc index e0a80d13bf..33c9c43eb4 100644 --- a/repos/base-hw/src/bootstrap/spec/arm_64/cortex_a53_mmu.cc +++ b/repos/base-hw/src/bootstrap/spec/arm_64/cortex_a53_mmu.cc @@ -199,6 +199,7 @@ unsigned Bootstrap::Platform::enable_mmu() Cpu::Sctlr::Sa0::set(sctlr, 1); Cpu::Sctlr::Sa::set(sctlr, 0); Cpu::Sctlr::Uct::set(sctlr, 1); + Cpu::Sctlr::Uci::set(sctlr, 1); Cpu::Sctlr_el1::write(sctlr); return cpu_id; diff --git a/repos/base-hw/src/include/hw/spec/arm_64/cpu.h b/repos/base-hw/src/include/hw/spec/arm_64/cpu.h index a3599a8dfd..7d6a6331d2 100644 --- a/repos/base-hw/src/include/hw/spec/arm_64/cpu.h +++ b/repos/base-hw/src/include/hw/spec/arm_64/cpu.h @@ -168,6 +168,7 @@ struct Hw::Arm_64_cpu struct I : Bitfield<12, 1> { }; struct Uct : Bitfield<15, 1> { }; struct Wxn : Bitfield<19, 1> { }; + struct Uci : Bitfield<26, 1> { }; }; SYSTEM_REGISTER(64, Sctlr_el1, sctlr_el1);