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hw: run core threads in privileged mode

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* introduce new syscall (core-only) to create privileged threads
* take the privilege level of the thread into account
  when doing a context switch
* map kernel segment as accessable for privileged code only

Ref #2091
This commit is contained in:
Stefan Kalkowski
2017-08-30 11:59:35 +02:00
committed by Christian Helmuth
parent 7e47fa58b3
commit ca60e24ad9
36 changed files with 222 additions and 112 deletions
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4
repos/base-hw/src/bootstrap/platform.cc
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@ -120,9 +120,9 @@ Mapping Platform::_load_elf()
phys = dst;
}
//FIXME: set read-only, privileged and global accordingly
//FIXME: set read-only accordingly
Page_flags flags{RW, segment.flags().x ? EXEC : NO_EXEC,
USER, GLOBAL, RAM, CACHED};
KERN, GLOBAL, RAM, CACHED};
Mapping m((addr_t)phys, (addr_t)segment.start(), size, flags);
/*

15
repos/base-hw/src/bootstrap/spec/arm/cpu.cc
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@ -24,16 +24,17 @@ void Bootstrap::Cpu::enable_mmu_and_caches(Genode::addr_t table)
/* do not use domains, but permission bits in table */
Dacr::write(Dacr::D0::bits(1));
Ttbcr::write(0);
Ttbcr::write(1);
Ttbr::access_t ttbr0 = Ttbr::Ba::masked(table);
Ttbr::Rgn::set(ttbr0, Ttbr::CACHEABLE);
Ttbr::access_t ttbr = Ttbr::Ba::masked(table);
Ttbr::Rgn::set(ttbr, Ttbr::CACHEABLE);
if (Mpidr::read()) { /* check for SMP system */
Ttbr::Irgn::set(ttbr0, Ttbr::CACHEABLE);
Ttbr::S::set(ttbr0, 1);
Ttbr::Irgn::set(ttbr, Ttbr::CACHEABLE);
Ttbr::S::set(ttbr, 1);
} else
Ttbr::C::set(ttbr0, 1);
Ttbr0::write(ttbr0);
Ttbr::C::set(ttbr, 1);
Ttbr0::write(ttbr);
Ttbr1::write(ttbr);
Sctlr::access_t sctlr = Sctlr::read();
Sctlr::C::set(sctlr, 1);

7
repos/base-hw/src/bootstrap/spec/riscv/platform.cc
View File

@ -12,6 +12,7 @@
* under the terms of the GNU Affero General Public License version 3.
*/
#include <platform.h>
#include <hw/spec/riscv/cpu.h>
using namespace Board;
@ -21,8 +22,6 @@ Bootstrap::Platform::Board::Board()
void Bootstrap::Platform::enable_mmu()
{
asm volatile ("csrw sptbr, %0\n" /* set asid | page table */
:
: "r" ((addr_t)core_pd->table_base >> 12)
: "memory");
using Sptbr = Hw::Riscv_cpu::Sptbr;
Sptbr::write(Sptbr::Ppn::masked((addr_t)core_pd->table_base >> 12));
}