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hw: use x86 exception stack unconditionally

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Always switch to the "exception stack" instead of having a hardware initiated
stack switch during exceptions/interrupts when the privilege level changes only.
Moreover, this commit increases the exception stack slightly.

Ref #2091
This commit is contained in:
Stefan Kalkowski 2017-08-30 11:34:21 +02:00 committed by Christian Helmuth
parent 42db1e112b
commit 7e47fa58b3
1 changed files with 17 additions and 17 deletions
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34
repos/base-hw/src/core/spec/x86_64/mode_transition.s
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@ -42,8 +42,8 @@
.set MT_IRQ_STACK, MT_BASE + (_mt_kernel_interrupt_stack - _mt_begin)
.set MT_ISR_ENTRY_SIZE, 12
.set IDT_FLAGS_PRIVILEGED, 0x8e00
.set IDT_FLAGS_UNPRIVILEGED, 0xee00
.set IDT_FLAGS_PRIVILEGED, 0x8e01
.set IDT_FLAGS_UNPRIVILEGED, 0xee01
.macro _isr_entry
.align 4, 0x90
@ -140,11 +140,21 @@
_mt_client_context_ptr:
.space CONTEXT_PTR_SIZE
/************************************************
** Temporary interrupt stack **
** Set as RSP for privilege levels 0-2 and as **
** IST1 in TSS, used by all IDT entries **
** See Intel SDM Vol. 3A, section 7.7 **
************************************************/
/* a globally mapped buffer per CPU */
.p2align 2
.p2align 4
.global _mt_buffer
_mt_buffer:
.space BUFFER_SIZE
.space 6 * BUFFER_SIZE
.global _mt_kernel_interrupt_stack
_mt_kernel_interrupt_stack:
.global _mt_kernel_entry_pic
_mt_kernel_entry_pic:
@ -282,22 +292,12 @@
.quad MT_IRQ_STACK
.quad MT_IRQ_STACK
.quad MT_IRQ_STACK
.space 76
.space 8
.quad MT_IRQ_STACK
.space 48
_define_gdt MT_TSS
/************************************************
** Temporary interrupt stack **
** Set as RSP for privilege levels 0-2 in TSS **
** See Intel SDM Vol. 3A, section 7.7 **
************************************************/
.p2align 8
.space 7 * 8
.global _mt_kernel_interrupt_stack
_mt_kernel_interrupt_stack:
/* end of the mode transition code */
.global _mt_end
_mt_end:
1: jmp 1b