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hw: add support for i.MX7 Dual SABRE board

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Fix #3251
This commit is contained in:
Stefan Kalkowski 2019-03-22 14:23:07 +01:00 committed by Norman Feske
parent 8f28f884ee
commit baf815d099
23 changed files with 638 additions and 49 deletions
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1
repos/base-hw/lib/mk/spec/exynos5/core-hw.inc
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@ -8,7 +8,6 @@
INC_DIR += $(BASE_DIR)/../base-hw/src/core/spec/exynos5
# add C++ sources
SRC_CC += spec/exynos5/cpu.cc
SRC_CC += spec/exynos5/timer.cc
# include less specific configuration

18
repos/base-hw/lib/mk/spec/imx7d_sabre/bootstrap-hw.mk Normal file
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@ -0,0 +1,18 @@
INC_DIR += $(BASE_DIR)/../base-hw/src/bootstrap/spec/imx7d_sabre
SRC_CC += bootstrap/spec/arm/cortex_a15_cpu.cc
SRC_CC += bootstrap/spec/arndale/pic.cc
SRC_CC += bootstrap/spec/imx7d_sabre/platform.cc
SRC_CC += bootstrap/spec/arm/arm_v7_cpu.cc
SRC_CC += hw/spec/32bit/memory_map.cc
SRC_S += bootstrap/spec/arm/crt0.s
NR_OF_CPUS = 2
#
# we need more specific compiler hints for some 'special' assembly code
# override -march=armv7-a because it conflicts with -mcpu=cortex-a7
#
CC_MARCH = -mcpu=cortex-a7 -mfpu=vfpv3 -mfloat-abi=softfp
include $(REP_DIR)/lib/mk/bootstrap-hw.inc

32
repos/base-hw/lib/mk/spec/imx7d_sabre/core-hw.mk Normal file
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@ -0,0 +1,32 @@
#
# \brief Build config for Genodes core process
# \author Stefan Kalkowski
# \date 2015-02-09
#
# add include paths
INC_DIR += $(REP_DIR)/src/core/spec/imx7d_sabre
INC_DIR += $(REP_DIR)/src/core/spec/arm_v7/virtualization
# add C++ sources
SRC_CC += spec/arm_gic/pic.cc
SRC_CC += spec/arndale/platform_services.cc
SRC_CC += spec/imx7d_sabre/timer.cc
SRC_CC += kernel/vm_thread_on.cc
SRC_CC += spec/arm_v7/virtualization/kernel/vm.cc
SRC_CC += spec/arm_v7/vm_session_component.cc
SRC_CC += spec/arm_v7/virtualization/vm_session_component.cc
# add assembly sources
SRC_S += spec/arm_v7/virtualization/exception_vector.s
NR_OF_CPUS = 2
#
# we need more specific compiler hints for some 'special' assembly code
# override -march=armv7-a because it conflicts with -mcpu=cortex-a7
#
CC_MARCH = -mcpu=cortex-a7 -mfpu=vfpv3 -mfloat-abi=softfp
# include less specific configuration
include $(BASE_DIR)/../base-hw/lib/mk/spec/cortex_a15/core-hw.inc

4
repos/base-hw/src/bootstrap/spec/arm/cortex_a15_cpu.cc
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@ -54,6 +54,10 @@ void Bootstrap::Cpu::enable_mmu_and_caches(Genode::addr_t table)
Ttbcr::Eae::set(ttbcr, 1);
Ttbcr::write(ttbcr);
/* toggle smp bit */
Actlr::access_t actlr = Actlr::read();
Actlr::write(actlr | (1 << 6));
Sctlr::access_t sctlr = Sctlr::read();
Sctlr::C::set(sctlr, 1);
Sctlr::I::set(sctlr, 1);

1
repos/base-hw/src/bootstrap/spec/arndale/platform.cc
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@ -21,7 +21,6 @@ using namespace Board;
Bootstrap::Platform::Board::Board()
: early_ram_regions(Memory_region { RAM_0_BASE, RAM_0_SIZE }),
core_mmio(Memory_region { IRQ_CONTROLLER_BASE, IRQ_CONTROLLER_SIZE },
Memory_region { IRQ_CONTROLLER_VT_CTRL_BASE, IRQ_CONTROLLER_VT_CTRL_SIZE },
Memory_region { MCT_MMIO_BASE, MCT_MMIO_SIZE },
Memory_region { UART_2_MMIO_BASE, UART_2_MMIO_SIZE }) { }

38
repos/base-hw/src/bootstrap/spec/imx7d_sabre/board.h Normal file
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@ -0,0 +1,38 @@
/*
* \brief Imx7 Sabrelite specific board definitions
* \author Stefan Kalkowski
* \date 2018-11-07
*/
/*
* Copyright (C) 2018 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _SRC__BOOTSTRAP__SPEC__IMX7_SABRELITE__BOARD_H_
#define _SRC__BOOTSTRAP__SPEC__IMX7_SABRELITE__BOARD_H_
#include <drivers/defs/imx7d_sabre.h>
#include <drivers/uart/imx.h>
#include <hw/spec/arm/cortex_a15.h>
#include <hw/spec/arm/lpae.h>
#include <spec/arm/cpu.h>
#include <spec/arm/pic.h>
namespace Board {
using namespace Imx7d_sabre;
using Cpu_mmio = Hw::Cortex_a15_mmio<IRQ_CONTROLLER_BASE>;
using Serial = Genode::Imx_uart;
enum {
UART_BASE = UART_1_MMIO_BASE,
UART_CLOCK = 0, /* unsued value */
};
}
#endif /* _SRC__BOOTSTRAP__SPEC__IMX&_SABRELITE__BOARD_H_ */

343
repos/base-hw/src/bootstrap/spec/imx7d_sabre/platform.cc Normal file
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@ -0,0 +1,343 @@
/*
* \brief Parts of platform that are specific to Imx7 sabrelite
* \author Stefan Kalkowski
* \date 2018-11-07
*/
/*
* Copyright (C) 2018 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#include <platform.h>
#include <spec/arm/imx_aipstz.h>
extern "C" void * _start_setup_stack; /* entrypoint for non-boot CPUs */
static unsigned char hyp_mode_stack[1024]; /* hypervisor mode's kernel stack */
using namespace Board;
Bootstrap::Platform::Board::Board()
: early_ram_regions(Memory_region { RAM_0_BASE, RAM_0_SIZE }),
core_mmio(Memory_region { IRQ_CONTROLLER_BASE, IRQ_CONTROLLER_SIZE },
Memory_region { UART_1_MMIO_BASE, UART_1_MMIO_SIZE })
{
Aipstz aipstz_1(AIPS_1_MMIO_BASE);
Aipstz aipstz_2(AIPS_2_MMIO_BASE);
Aipstz aipstz_3(AIPS_3_MMIO_BASE);
/* configure CSU */
for (addr_t start = 0x303e0000; start <= 0x303e00fc; start += 4)
*(volatile addr_t *)start = 0x00ff00ff;
static volatile unsigned long initial_values[][2] {
// CCM (Clock Control Module)
{ 0x30384000, 0x3 },
{ 0x30384040, 0x3 },
{ 0x30384060, 0x3 },
{ 0x30384130, 0x3 },
{ 0x30384160, 0x0 },
{ 0x303844f0, 0x3 },
{ 0x30384510, 0x0 },
{ 0x30384520, 0x3 },
{ 0x303846d0, 0x0 },
{ 0x303846e0, 0x0 },
{ 0x30384780, 0x0 },
{ 0x30384790, 0x0 },
{ 0x303847a0, 0x0 },
{ 0x303847b0, 0x0 },
{ 0x303847c0, 0x3 },
{ 0x30384880, 0x0 },
{ 0x303848a0, 0x0 },
{ 0x30384950, 0x0 },
{ 0x30384960, 0x0 },
{ 0x30384970, 0x0 },
{ 0x30384980, 0x0 },
{ 0x30384990, 0x0 },
{ 0x303849a0, 0x0 },
{ 0x303849d0, 0x0 },
{ 0x303849e0, 0x0 },
{ 0x303849f0, 0x0 },
{ 0x303600c0, 0xd2605a56 },
{ 0x303600d0, 0xd2d2d256 },
{ 0x303600d4, 0xd2d2d256 },
{ 0x303600d8, 0xd2d2d256 },
{ 0x303600dc, 0xd2d2d256 },
{ 0x303600e0, 0x80000600 },
{ 0x303600f0, 0x101b },
// IOMUXC (IOMUX Controller)
{ 0x30330030, 0x14 },
{ 0x30330034, 0x10 },
{ 0x30330074, 0x2 },
{ 0x30330078, 0x2 },
{ 0x3033007c, 0x2 },
{ 0x30330080, 0x2 },
{ 0x30330084, 0x2 },
{ 0x30330088, 0x2 },
{ 0x3033008c, 0x2 },
{ 0x30330090, 0x2 },
{ 0x30330094, 0x2 },
{ 0x30330098, 0x2 },
{ 0x3033009c, 0x2 },
{ 0x303300a0, 0x2 },
{ 0x303300c4, 0x0 },
{ 0x30330150, 0x10 },
{ 0x30330154, 0x10 },
{ 0x30330210, 0x13 },
{ 0x30330214, 0x13 },
{ 0x3033021c, 0x1 },
{ 0x30330220, 0x1 },
{ 0x30330224, 0x1 },
{ 0x303302e4, 0x1 },
{ 0x303302e8, 0x1 },
{ 0x303302ec, 0x1 },
{ 0x303302f0, 0x1 },
{ 0x303302f4, 0x1 },
{ 0x303302f8, 0x1 },
{ 0x303302fc, 0x1 },
{ 0x30330300, 0x1 },
{ 0x30330304, 0x1 },
{ 0x30330308, 0x1 },
{ 0x3033030c, 0x1 },
{ 0x30330310, 0x1 },
{ 0x30330318, 0x59 },
{ 0x303303c0, 0x7f },
{ 0x303303c4, 0x7f },
{ 0x303303f4, 0x34 },
{ 0x303303f8, 0x59 },
{ 0x303303fc, 0x59 },
{ 0x30330400, 0x59 },
{ 0x30330404, 0x19 },
{ 0x30330408, 0x59 },
{ 0x3033040c, 0x59 },
{ 0x30330410, 0x59 },
{ 0x30330414, 0x59 },
{ 0x30330418, 0x59 },
{ 0x3033041c, 0x59 },
{ 0x30330440, 0x19 },
{ 0x30330444, 0x59 },
{ 0x30330448, 0x59 },
{ 0x3033044c, 0x59 },
{ 0x30330450, 0x59 },
{ 0x30330454, 0x59 },
{ 0x30330458, 0x59 },
{ 0x3033045c, 0x59 },
{ 0x30330460, 0x59 },
{ 0x30330464, 0x59 },
{ 0x30330468, 0x19 },
{ 0x30330480, 0x7f },
{ 0x30330484, 0x7f },
{ 0x3033048c, 0x2 },
{ 0x30330490, 0x2 },
{ 0x30330494, 0x2 },
{ 0x3033049c, 0x1 },
{ 0x303304a0, 0x1 },
{ 0x303304a4, 0x1 },
{ 0x303304a8, 0x1 },
{ 0x303304ac, 0x1 },
{ 0x303304b0, 0x1 },
{ 0x303304b4, 0x1 },
{ 0x303304b8, 0x1 },
{ 0x303304bc, 0x1 },
{ 0x303304c0, 0x1 },
{ 0x303304c4, 0x1 },
{ 0x303304c8, 0x1 },
{ 0x30330544, 0x1 },
{ 0x30330548, 0x1 },
{ 0x3033054c, 0x1 },
{ 0x303305dc, 0x1 },
{ 0x303305e0, 0x1 },
{ 0x303305ec, 0x3 },
{ 0x303305f0, 0x3 }
};
unsigned num_values = sizeof(initial_values) / (2*sizeof(unsigned long));
for (unsigned i = 0; i < num_values; i++)
*((volatile unsigned long*)initial_values[i][0]) = initial_values[i][1];
}
static inline void prepare_nonsecure_world(unsigned long timer_freq)
{
using Cpu = Hw::Arm_cpu;
/* if we are already in HYP mode we're done (depends on u-boot version) */
if (Cpu::Psr::M::get(Cpu::Cpsr::read()) == Cpu::Psr::M::HYP)
return;
/* ARM generic timer counter freq needs to be set in secure mode */
Cpu::Cntfrq::write(timer_freq);
/*
* enable coprocessor 10 + 11 access and SMP bit access in auxiliary control
* register for non-secure world
*/
Cpu::Nsacr::access_t nsacr = 0;
Cpu::Nsacr::Cpnsae10::set(nsacr, 1);
Cpu::Nsacr::Cpnsae11::set(nsacr, 1);
Cpu::Nsacr::Ns_smp::set(nsacr, 1);
Cpu::Nsacr::write(nsacr);
asm volatile (
"msr sp_mon, sp \n" /* copy current mode's sp */
"msr lr_mon, lr \n" /* copy current mode's lr */
"cps #22 \n" /* switch to monitor mode */
);
Cpu::Scr::access_t scr = 0;
Cpu::Scr::Ns::set(scr, 1);
Cpu::Scr::Fw::set(scr, 1);
Cpu::Scr::Aw::set(scr, 1);
Cpu::Scr::Scd::set(scr, 1);
Cpu::Scr::Hce::set(scr, 1);
Cpu::Scr::Sif::set(scr, 1);
Cpu::Scr::write(scr);
}
static inline void prepare_hypervisor(Genode::addr_t table)
{
using Cpu = Hw::Arm_cpu;
/* set hypervisor exception vector */
Cpu::Hvbar::write(Hw::Mm::hypervisor_exception_vector().base);
/* set hypervisor's translation table */
Cpu::Httbr_64bit::write(table);
Cpu::Ttbcr::access_t ttbcr = 0;
Cpu::Ttbcr::Irgn0::set(ttbcr, 1);
Cpu::Ttbcr::Orgn0::set(ttbcr, 1);
Cpu::Ttbcr::Sh0::set(ttbcr, 2);
Cpu::Ttbcr::Eae::set(ttbcr, 1);
/* prepare MMU usage by hypervisor code */
Cpu::Htcr::write(ttbcr);
/* don't trap on cporocessor 10 + 11, but all others */
Cpu::Hcptr::access_t hcptr = 0;
Cpu::Hcptr::Tcp<0>::set(hcptr, 1);
Cpu::Hcptr::Tcp<1>::set(hcptr, 1);
Cpu::Hcptr::Tcp<2>::set(hcptr, 1);
Cpu::Hcptr::Tcp<3>::set(hcptr, 1);
Cpu::Hcptr::Tcp<4>::set(hcptr, 1);
Cpu::Hcptr::Tcp<5>::set(hcptr, 1);
Cpu::Hcptr::Tcp<6>::set(hcptr, 1);
Cpu::Hcptr::Tcp<7>::set(hcptr, 1);
Cpu::Hcptr::Tcp<8>::set(hcptr, 1);
Cpu::Hcptr::Tcp<9>::set(hcptr, 1);
Cpu::Hcptr::Tcp<12>::set(hcptr, 1);
Cpu::Hcptr::Tcp<13>::set(hcptr, 1);
Cpu::Hcptr::Tta::set(hcptr, 1);
Cpu::Hcptr::Tcpac::set(hcptr, 1);
Cpu::Hcptr::write(hcptr);
enum Memory_attributes {
DEVICE_MEMORY = 0x04,
NORMAL_MEMORY_UNCACHED = 0x44,
NORMAL_MEMORY_CACHED = 0xff,
};
Cpu::Mair0::access_t mair0 = 0;
Cpu::Mair0::Attr0::set(mair0, NORMAL_MEMORY_UNCACHED);
Cpu::Mair0::Attr1::set(mair0, DEVICE_MEMORY);
Cpu::Mair0::Attr2::set(mair0, NORMAL_MEMORY_CACHED);
Cpu::Mair0::Attr3::set(mair0, DEVICE_MEMORY);
Cpu::Hmair0::write(mair0);
Cpu::Vtcr::access_t vtcr = ttbcr;
Cpu::Vtcr::Sl0::set(vtcr, 1); /* set to starting level 1 */
Cpu::Vtcr::write(vtcr);
Cpu::Sctlr::access_t sctlr = Cpu::Sctlr::read();
Cpu::Sctlr::C::set(sctlr, 1);
Cpu::Sctlr::I::set(sctlr, 1);
Cpu::Sctlr::V::set(sctlr, 1);
Cpu::Sctlr::A::set(sctlr, 0);
Cpu::Sctlr::M::set(sctlr, 1);
Cpu::Sctlr::Z::set(sctlr, 1);
Cpu::Hsctlr::write(sctlr);
}
static inline void switch_to_supervisor_mode()
{
using Cpsr = Hw::Arm_cpu::Psr;
Cpsr::access_t cpsr = 0;
Cpsr::M::set(cpsr, Cpsr::M::SVC);
Cpsr::F::set(cpsr, 1);
Cpsr::I::set(cpsr, 1);
asm volatile (
"msr sp_svc, sp \n" /* copy current mode's sp */
"msr lr_svc, lr \n" /* copy current mode's lr */
"msr elr_hyp, lr \n" /* copy current mode's lr to hyp lr */
"msr sp_hyp, %[stack] \n" /* copy to hyp stack pointer */
"msr spsr_cxfs, %[cpsr] \n" /* set psr for supervisor mode */
"adr lr, 1f \n" /* load exception return address */
"eret \n" /* exception return */
"1:":: [cpsr] "r" (cpsr), [stack] "r" (&hyp_mode_stack));
}
unsigned Bootstrap::Platform::enable_mmu()
{
static volatile bool primary_cpu = true;
static unsigned long timer_freq = Cpu::Cntfrq::read();
pic.init_cpu_local();
prepare_nonsecure_world(timer_freq);
prepare_hypervisor((addr_t)core_pd->table_base);
switch_to_supervisor_mode();
Cpu::Sctlr::init();
Cpu::Cpsr::init();
/* primary cpu wakes up all others */
if (primary_cpu && NR_OF_CPUS > 1) {
cpu.invalidate_data_cache();
primary_cpu = false;
cpu.wake_up_all_cpus(&_start_setup_stack);
}
cpu.enable_mmu_and_caches((Genode::addr_t)core_pd->table_base);
return Cpu::Mpidr::Aff_0::get(Cpu::Mpidr::read());
}
void Bootstrap::Cpu::wake_up_all_cpus(void * const ip)
{
struct Src : Genode::Mmio
{
struct A7_cr0 : Register<0x4, 32>
{
struct Core1_por_reset : Bitfield<1,1> {};
struct Core1_soft_reset : Bitfield<5,1> {};
};
struct A7_cr1 : Register<0x8, 32>
{
struct Core1_enable : Bitfield<1,1> {};
};
struct Gpr3 : Register<0x7c, 32> {}; /* ep core 1 */
struct Gpr4 : Register<0x80, 32> {}; /* ep core 1 */
Src(void * const entry) : Genode::Mmio(SRC_MMIO_BASE)
{
write<Gpr3>((Gpr3::access_t)entry);
write<Gpr4>((Gpr4::access_t)entry);
A7_cr0::access_t v0 = read<A7_cr0>();
A7_cr0::Core1_soft_reset::set(v0,1);
write<A7_cr0>(v0);
A7_cr1::access_t v1 = read<A7_cr1>();
A7_cr1::Core1_enable::set(v1,1);
write<A7_cr1>(v1);
}
};
Src src(ip);
}

2
repos/base-hw/src/core/kernel/cpu.h
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@ -134,6 +134,8 @@ class Kernel::Cpu : public Genode::Cpu, private Irq::Pool, private Timeout
Cpu(unsigned const id, Pic & pic,
Inter_processor_work_list & global_work_list);
static inline unsigned primary_id() { return 0; }
/**
* Raise the IPI of the CPU
*/

2
repos/base-hw/src/core/platform_thread.cc
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@ -163,7 +163,7 @@ int Platform_thread::start(void * const ip, void * const sp)
}
unsigned const cpu =
_location.valid() ? _location.xpos() : Cpu::primary_id();
_location.valid() ? _location.xpos() : 0;
Native_utcb &utcb = *Thread::myself()->utcb();

5
repos/base-hw/src/core/spec/arm/cpu_support.h
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@ -155,11 +155,6 @@ struct Genode::Arm_cpu : public Hw::Arm_cpu
* Return kernel name of the executing CPU
*/
static unsigned executing_id() { return 0; }
/**
* Return kernel name of the primary CPU
*/
static unsigned primary_id() { return 0; }
};
#endif /* _CORE__SPEC__ARM__CPU_SUPPORT_H_ */

2
repos/base-hw/src/core/spec/arm_v7/virtualization/kernel/vm.cc
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@ -92,7 +92,7 @@ struct Kernel::Virtual_pic : Genode::Mmio
Vm_irq irq { Board::VT_MAINTAINANCE_IRQ };
Virtual_pic()
: Genode::Mmio(Genode::Platform::mmio_to_virt(Board::IRQ_CONTROLLER_VT_CTRL_BASE)) { }
: Genode::Mmio(Genode::Platform::mmio_to_virt(Board::Cpu_mmio::IRQ_CONTROLLER_VT_CTRL_BASE)) { }
static Virtual_pic& pic()
{

4
repos/base-hw/src/core/spec/arm_v7/virtualization/vm_session_component.cc
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@ -70,8 +70,8 @@ void Vm_session_component::attach(Dataspace_capability ds_cap, addr_t vm_addr)
void Vm_session_component::attach_pic(addr_t vm_addr)
{
_attach(Board::IRQ_CONTROLLER_VT_CPU_BASE, vm_addr,
Board::IRQ_CONTROLLER_VT_CPU_SIZE);
_attach(Board::Cpu_mmio::IRQ_CONTROLLER_VT_CPU_BASE, vm_addr,
Board::Cpu_mmio::IRQ_CONTROLLER_VT_CPU_SIZE);
}

4
repos/base-hw/src/core/spec/cortex_a15/cpu.h
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@ -113,10 +113,6 @@ class Genode::Cpu : public Arm_v7_cpu
*/
static unsigned executing_id() { return Mpidr::Aff_0::get(Mpidr::read()); }
/**
* Return kernel name of the primary CPU
*/
static unsigned primary_id();
void switch_to(Context &, Mmu_context & mmu_context)
{

21
repos/base-hw/src/core/spec/exynos5/cpu.cc
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@ -1,21 +0,0 @@
/*
* \brief CPU driver for core
* \author Martin stein
* \author Stefan Kalkowski
* \date 2011-11-03
*/
/*
* Copyright (C) 2011-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
/* core includes */
#include <board.h>
#include <cpu.h>
using namespace Genode;
unsigned Cpu::primary_id() { return Board::PRIMARY_MPIDR_AFF_0; }

36
repos/base-hw/src/core/spec/imx7d_sabre/board.h Normal file
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@ -0,0 +1,36 @@
/*
* \brief Board driver for core
* \author Stefan Kalkowski
* \date 2018-11-07
*/
/*
* Copyright (C) 2018 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _CORE__SPEC__IMX7D_SABRE__BOARD_H_
#define _CORE__SPEC__IMX7D_SABRE__BOARD_H_
/* base includes */
#include <drivers/defs/imx7d_sabre.h>
#include <drivers/uart/imx.h>
#include <hw/spec/arm/cortex_a15.h>
namespace Board {
using namespace Imx7d_sabre;
using Cpu_mmio = Hw::Cortex_a15_mmio<IRQ_CONTROLLER_BASE>;
using Serial = Genode::Imx_uart;
enum {
UART_BASE = UART_1_MMIO_BASE,
UART_CLOCK = 0, /* unused value */
};
static constexpr bool SMP = true;
}
#endif /* _CORE__SPEC__IMX7_SABRELITE__BOARD_H_ */

75
repos/base-hw/src/core/spec/imx7d_sabre/timer.cc Normal file
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@ -0,0 +1,75 @@
/*
* \brief Timer driver for core
* \author Stefan Kalkowski
* \author Martin stein
* \date 2013-01-10
*/
/*
* Copyright (C) 2013-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#include <drivers/timer/util.h>
#include <kernel/timer.h>
#include <board.h>
#include <platform.h>
using namespace Genode;
using namespace Kernel;
unsigned Timer::interrupt_id() const
{
return 30;
}
unsigned long Timer_driver::_freq()
{
unsigned long freq;
asm volatile("mrc p15, 0, %0, c14, c0, 0\n" : "=r" (freq));
return freq;
}
Timer_driver::Timer_driver(unsigned) : ticks_per_ms(_freq() / 1000)
{
unsigned long ctrl;
asm volatile("mrc p15, 0, %0, c14, c2, 1\n" : "=r" (ctrl));
asm volatile("mcr p15, 0, %0, c14, c2, 1\n" :: "r" (ctrl | 1));
}
void Timer::_start_one_shot(time_t const ticks)
{
unsigned long ctrl;
unsigned long v0, v1;
asm volatile("mrrc p15, 0, %0, %1, c14\n" : "=r" (v0), "=r" (v1));
_driver.last_time = (Genode::uint64_t)v0 | (Genode::uint64_t)v1 << 32;
asm volatile("mcr p15, 0, %0, c14, c2, 0\n" :: "r" (ticks));
asm volatile("mrc p15, 0, %0, c14, c2, 1\n" : "=r" (ctrl));
asm volatile("mcr p15, 0, %0, c14, c2, 1\n" :: "r" (ctrl & ~4UL));
}
time_t Timer::_duration() const
{
unsigned long v0, v1;
asm volatile("mrrc p15, 0, %0, %1, c14\n" : "=r" (v0), "=r" (v1));
Genode::uint64_t v = (Genode::uint64_t)v0 | (Genode::uint64_t)v1 << 32;
return v - _driver.last_time;
}
time_t Timer::ticks_to_us(time_t const ticks) const {
return timer_ticks_to_us(ticks, _driver.ticks_per_ms); }
time_t Timer::us_to_ticks(time_t const us) const {
return (us / 1000) * _driver.ticks_per_ms; }
time_t Timer::_max_value() const {
return _driver.ticks_per_ms * 5000; }

34
repos/base-hw/src/core/spec/imx7d_sabre/timer_driver.h Normal file
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@ -0,0 +1,34 @@
/*
* \brief Timer driver for core
* \author Martin stein
* \date 2013-01-10
*/
/*
* Copyright (C) 2013-2017 Genode Labs GmbH
*
* This file is part of the Kernel OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _TIMER_DRIVER_H_
#define _TIMER_DRIVER_H_
/* base-hw includes */
#include <kernel/types.h>
namespace Kernel { class Timer_driver; }
struct Kernel::Timer_driver
{
unsigned long _freq();
unsigned const ticks_per_ms;
time_t last_time { 0 };
Timer_driver(unsigned);
};
#endif /* _TIMER_DRIVER_H_ */

1
repos/base-hw/src/core/spec/riscv/cpu.h
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@ -81,7 +81,6 @@ class Genode::Cpu : public Hw::Riscv_cpu
static void mmu_fault(Context & c, Kernel::Thread_fault & f);
static unsigned executing_id() { return 0; }
static unsigned primary_id() { return 0; }
};
#endif /* _CORE__SPEC__RISCV__CPU_H_ */

5
repos/base-hw/src/core/spec/x86_64/cpu.h
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@ -121,11 +121,6 @@ class Genode::Cpu : public Hw::X86_64_cpu
*/
static unsigned executing_id();
/**
* Return kernel name of the primary CPU
*/
static unsigned primary_id() { return 0; }
/**
* Switch to new context
*

11
repos/base-hw/src/lib/hw/spec/arm/cortex_a15.h
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@ -22,10 +22,13 @@ template <typename Genode::addr_t BASE>
struct Hw::Cortex_a15_mmio
{
enum {
IRQ_CONTROLLER_DISTR_BASE = BASE + 0x1000,
IRQ_CONTROLLER_DISTR_SIZE = 0x1000,
IRQ_CONTROLLER_CPU_BASE = BASE + 0x2000,
IRQ_CONTROLLER_CPU_SIZE = 0x2000,
IRQ_CONTROLLER_DISTR_BASE = BASE + 0x1000UL,
IRQ_CONTROLLER_DISTR_SIZE = 0x1000UL,
IRQ_CONTROLLER_CPU_BASE = BASE + 0x2000UL,
IRQ_CONTROLLER_CPU_SIZE = 0x2000UL,
IRQ_CONTROLLER_VT_CTRL_BASE = BASE + 0x4000UL,
IRQ_CONTROLLER_VT_CPU_BASE = BASE + 0x6000UL,
IRQ_CONTROLLER_VT_CPU_SIZE = 0x1000UL,
};
};

3
repos/base/include/drivers/defs/exynos5.h
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@ -60,9 +60,6 @@ namespace Exynos5 {
/* IRAM */
IRAM_BASE = 0x02020000,
/* hardware name of the primary processor */
PRIMARY_MPIDR_AFF_0 = 0,
/* SATA/AHCI */
SATA_IRQ = 147,

44
repos/base/include/drivers/defs/imx7d_sabre.h Normal file
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@ -0,0 +1,44 @@
/*
* \brief Definitions for the Imx7 dual sabre board
* \author Stefan Kalkowski
* \date 2018-10-07
*/
/*
* Copyright (C) 2018 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _INCLUDE__DRIVERS__DEFS__IMX7D_SABRE_H_
#define _INCLUDE__DRIVERS__DEFS__IMX7D_SABRE_H_
namespace Imx7d_sabre {
enum {
RAM_0_BASE = 0x80000000UL,
RAM_0_SIZE = 0x40000000UL,
IRQ_CONTROLLER_BASE = 0x31000000UL,
IRQ_CONTROLLER_SIZE = 0x8000,
SRC_MMIO_BASE = 0x30390000UL,
AIPS_1_MMIO_BASE = 0x301f0000UL,
AIPS_2_MMIO_BASE = 0x305f0000UL,
AIPS_3_MMIO_BASE = 0x309f0000UL,
UART_1_MMIO_BASE = 0x30860000UL,
UART_1_MMIO_SIZE = 0x10000UL,
TIMER_CLOCK = 1000000000UL,
CACHE_LINE_SIZE_LOG2 = 6,
VT_MAINTAINANCE_IRQ,
VT_TIMER_IRQ,
};
}
#endif /* _INCLUDE__DRIVERS__DEFS__IMX7D_SABRE_H_ */

1
tool/run/boot_dir/hw
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@ -13,6 +13,7 @@ proc bootstrap_link_address { } {
if {[have_spec "wand_quad"]} { return "0x10001000" }
if {[have_spec "imx6q_sabrelite"]} { return "0x10001000" }
if {[have_spec "imx53_qsb"]} { return "0x70010000" }
if {[have_spec "imx7d_sabre"]} { return "0x88000000" }
if {[have_spec "arndale"]} { return "0x88000000" }
if {[have_spec "panda"]} { return "0x88000000" }
if {[have_spec "zynq"]} { return "0x00100000" }