From baf815d09986a15d72224a418503919c36d7a986 Mon Sep 17 00:00:00 2001 From: Stefan Kalkowski Date: Fri, 22 Mar 2019 14:23:07 +0100 Subject: [PATCH] hw: add support for i.MX7 Dual SABRE board Fix #3251 --- repos/base-hw/lib/mk/spec/exynos5/core-hw.inc | 1 - .../lib/mk/spec/imx7d_sabre/bootstrap-hw.mk | 18 + .../lib/mk/spec/imx7d_sabre/core-hw.mk | 32 ++ .../src/bootstrap/spec/arm/cortex_a15_cpu.cc | 4 + .../src/bootstrap/spec/arndale/platform.cc | 1 - .../src/bootstrap/spec/imx7d_sabre/board.h | 38 ++ .../bootstrap/spec/imx7d_sabre/platform.cc | 343 ++++++++++++++++++ repos/base-hw/src/core/kernel/cpu.h | 2 + repos/base-hw/src/core/platform_thread.cc | 2 +- repos/base-hw/src/core/spec/arm/cpu_support.h | 5 - .../spec/arm_v7/virtualization/kernel/vm.cc | 2 +- .../virtualization/vm_session_component.cc | 4 +- repos/base-hw/src/core/spec/cortex_a15/cpu.h | 4 - repos/base-hw/src/core/spec/exynos5/cpu.cc | 21 -- .../base-hw/src/core/spec/imx7d_sabre/board.h | 36 ++ .../src/core/spec/imx7d_sabre/timer.cc | 75 ++++ .../src/core/spec/imx7d_sabre/timer_driver.h | 34 ++ repos/base-hw/src/core/spec/riscv/cpu.h | 1 - repos/base-hw/src/core/spec/x86_64/cpu.h | 5 - .../base-hw/src/lib/hw/spec/arm/cortex_a15.h | 11 +- repos/base/include/drivers/defs/exynos5.h | 3 - repos/base/include/drivers/defs/imx7d_sabre.h | 44 +++ tool/run/boot_dir/hw | 1 + 23 files changed, 638 insertions(+), 49 deletions(-) create mode 100644 repos/base-hw/lib/mk/spec/imx7d_sabre/bootstrap-hw.mk create mode 100644 repos/base-hw/lib/mk/spec/imx7d_sabre/core-hw.mk create mode 100644 repos/base-hw/src/bootstrap/spec/imx7d_sabre/board.h create mode 100644 repos/base-hw/src/bootstrap/spec/imx7d_sabre/platform.cc delete mode 100644 repos/base-hw/src/core/spec/exynos5/cpu.cc create mode 100644 repos/base-hw/src/core/spec/imx7d_sabre/board.h create mode 100644 repos/base-hw/src/core/spec/imx7d_sabre/timer.cc create mode 100644 repos/base-hw/src/core/spec/imx7d_sabre/timer_driver.h create mode 100644 repos/base/include/drivers/defs/imx7d_sabre.h diff --git a/repos/base-hw/lib/mk/spec/exynos5/core-hw.inc b/repos/base-hw/lib/mk/spec/exynos5/core-hw.inc index f9d139ace6..79d69409f9 100644 --- a/repos/base-hw/lib/mk/spec/exynos5/core-hw.inc +++ b/repos/base-hw/lib/mk/spec/exynos5/core-hw.inc @@ -8,7 +8,6 @@ INC_DIR += $(BASE_DIR)/../base-hw/src/core/spec/exynos5 # add C++ sources -SRC_CC += spec/exynos5/cpu.cc SRC_CC += spec/exynos5/timer.cc # include less specific configuration diff --git a/repos/base-hw/lib/mk/spec/imx7d_sabre/bootstrap-hw.mk b/repos/base-hw/lib/mk/spec/imx7d_sabre/bootstrap-hw.mk new file mode 100644 index 0000000000..85fe91397f --- /dev/null +++ b/repos/base-hw/lib/mk/spec/imx7d_sabre/bootstrap-hw.mk @@ -0,0 +1,18 @@ +INC_DIR += $(BASE_DIR)/../base-hw/src/bootstrap/spec/imx7d_sabre + +SRC_CC += bootstrap/spec/arm/cortex_a15_cpu.cc +SRC_CC += bootstrap/spec/arndale/pic.cc +SRC_CC += bootstrap/spec/imx7d_sabre/platform.cc +SRC_CC += bootstrap/spec/arm/arm_v7_cpu.cc +SRC_CC += hw/spec/32bit/memory_map.cc +SRC_S += bootstrap/spec/arm/crt0.s + +NR_OF_CPUS = 2 + +# +# we need more specific compiler hints for some 'special' assembly code +# override -march=armv7-a because it conflicts with -mcpu=cortex-a7 +# +CC_MARCH = -mcpu=cortex-a7 -mfpu=vfpv3 -mfloat-abi=softfp + +include $(REP_DIR)/lib/mk/bootstrap-hw.inc diff --git a/repos/base-hw/lib/mk/spec/imx7d_sabre/core-hw.mk b/repos/base-hw/lib/mk/spec/imx7d_sabre/core-hw.mk new file mode 100644 index 0000000000..3d7c762f71 --- /dev/null +++ b/repos/base-hw/lib/mk/spec/imx7d_sabre/core-hw.mk @@ -0,0 +1,32 @@ +# +# \brief Build config for Genodes core process +# \author Stefan Kalkowski +# \date 2015-02-09 +# + +# add include paths +INC_DIR += $(REP_DIR)/src/core/spec/imx7d_sabre +INC_DIR += $(REP_DIR)/src/core/spec/arm_v7/virtualization + +# add C++ sources +SRC_CC += spec/arm_gic/pic.cc +SRC_CC += spec/arndale/platform_services.cc +SRC_CC += spec/imx7d_sabre/timer.cc +SRC_CC += kernel/vm_thread_on.cc +SRC_CC += spec/arm_v7/virtualization/kernel/vm.cc +SRC_CC += spec/arm_v7/vm_session_component.cc +SRC_CC += spec/arm_v7/virtualization/vm_session_component.cc + +# add assembly sources +SRC_S += spec/arm_v7/virtualization/exception_vector.s + +NR_OF_CPUS = 2 + +# +# we need more specific compiler hints for some 'special' assembly code +# override -march=armv7-a because it conflicts with -mcpu=cortex-a7 +# +CC_MARCH = -mcpu=cortex-a7 -mfpu=vfpv3 -mfloat-abi=softfp + +# include less specific configuration +include $(BASE_DIR)/../base-hw/lib/mk/spec/cortex_a15/core-hw.inc diff --git a/repos/base-hw/src/bootstrap/spec/arm/cortex_a15_cpu.cc b/repos/base-hw/src/bootstrap/spec/arm/cortex_a15_cpu.cc index 764499102c..aa1fc1d29b 100644 --- a/repos/base-hw/src/bootstrap/spec/arm/cortex_a15_cpu.cc +++ b/repos/base-hw/src/bootstrap/spec/arm/cortex_a15_cpu.cc @@ -54,6 +54,10 @@ void Bootstrap::Cpu::enable_mmu_and_caches(Genode::addr_t table) Ttbcr::Eae::set(ttbcr, 1); Ttbcr::write(ttbcr); + /* toggle smp bit */ + Actlr::access_t actlr = Actlr::read(); + Actlr::write(actlr | (1 << 6)); + Sctlr::access_t sctlr = Sctlr::read(); Sctlr::C::set(sctlr, 1); Sctlr::I::set(sctlr, 1); diff --git a/repos/base-hw/src/bootstrap/spec/arndale/platform.cc b/repos/base-hw/src/bootstrap/spec/arndale/platform.cc index 35603fd221..0f530085b7 100644 --- a/repos/base-hw/src/bootstrap/spec/arndale/platform.cc +++ b/repos/base-hw/src/bootstrap/spec/arndale/platform.cc @@ -21,7 +21,6 @@ using namespace Board; Bootstrap::Platform::Board::Board() : early_ram_regions(Memory_region { RAM_0_BASE, RAM_0_SIZE }), core_mmio(Memory_region { IRQ_CONTROLLER_BASE, IRQ_CONTROLLER_SIZE }, - Memory_region { IRQ_CONTROLLER_VT_CTRL_BASE, IRQ_CONTROLLER_VT_CTRL_SIZE }, Memory_region { MCT_MMIO_BASE, MCT_MMIO_SIZE }, Memory_region { UART_2_MMIO_BASE, UART_2_MMIO_SIZE }) { } diff --git a/repos/base-hw/src/bootstrap/spec/imx7d_sabre/board.h b/repos/base-hw/src/bootstrap/spec/imx7d_sabre/board.h new file mode 100644 index 0000000000..e17bd05789 --- /dev/null +++ b/repos/base-hw/src/bootstrap/spec/imx7d_sabre/board.h @@ -0,0 +1,38 @@ +/* + * \brief Imx7 Sabrelite specific board definitions + * \author Stefan Kalkowski + * \date 2018-11-07 + */ + +/* + * Copyright (C) 2018 Genode Labs GmbH + * + * This file is part of the Genode OS framework, which is distributed + * under the terms of the GNU Affero General Public License version 3. + */ + +#ifndef _SRC__BOOTSTRAP__SPEC__IMX7_SABRELITE__BOARD_H_ +#define _SRC__BOOTSTRAP__SPEC__IMX7_SABRELITE__BOARD_H_ + +#include +#include + +#include +#include +#include +#include + +namespace Board { + + using namespace Imx7d_sabre; + + using Cpu_mmio = Hw::Cortex_a15_mmio; + using Serial = Genode::Imx_uart; + + enum { + UART_BASE = UART_1_MMIO_BASE, + UART_CLOCK = 0, /* unsued value */ + }; +} + +#endif /* _SRC__BOOTSTRAP__SPEC__IMX&_SABRELITE__BOARD_H_ */ diff --git a/repos/base-hw/src/bootstrap/spec/imx7d_sabre/platform.cc b/repos/base-hw/src/bootstrap/spec/imx7d_sabre/platform.cc new file mode 100644 index 0000000000..0767241401 --- /dev/null +++ b/repos/base-hw/src/bootstrap/spec/imx7d_sabre/platform.cc @@ -0,0 +1,343 @@ +/* + * \brief Parts of platform that are specific to Imx7 sabrelite + * \author Stefan Kalkowski + * \date 2018-11-07 + */ + +/* + * Copyright (C) 2018 Genode Labs GmbH + * + * This file is part of the Genode OS framework, which is distributed + * under the terms of the GNU Affero General Public License version 3. + */ + +#include +#include + +extern "C" void * _start_setup_stack; /* entrypoint for non-boot CPUs */ +static unsigned char hyp_mode_stack[1024]; /* hypervisor mode's kernel stack */ + +using namespace Board; + +Bootstrap::Platform::Board::Board() +: early_ram_regions(Memory_region { RAM_0_BASE, RAM_0_SIZE }), + core_mmio(Memory_region { IRQ_CONTROLLER_BASE, IRQ_CONTROLLER_SIZE }, + Memory_region { UART_1_MMIO_BASE, UART_1_MMIO_SIZE }) +{ + Aipstz aipstz_1(AIPS_1_MMIO_BASE); + Aipstz aipstz_2(AIPS_2_MMIO_BASE); + Aipstz aipstz_3(AIPS_3_MMIO_BASE); + + /* configure CSU */ + for (addr_t start = 0x303e0000; start <= 0x303e00fc; start += 4) + *(volatile addr_t *)start = 0x00ff00ff; + + static volatile unsigned long initial_values[][2] { + // CCM (Clock Control Module) + { 0x30384000, 0x3 }, + { 0x30384040, 0x3 }, + { 0x30384060, 0x3 }, + { 0x30384130, 0x3 }, + { 0x30384160, 0x0 }, + { 0x303844f0, 0x3 }, + { 0x30384510, 0x0 }, + { 0x30384520, 0x3 }, + { 0x303846d0, 0x0 }, + { 0x303846e0, 0x0 }, + { 0x30384780, 0x0 }, + { 0x30384790, 0x0 }, + { 0x303847a0, 0x0 }, + { 0x303847b0, 0x0 }, + { 0x303847c0, 0x3 }, + { 0x30384880, 0x0 }, + { 0x303848a0, 0x0 }, + { 0x30384950, 0x0 }, + { 0x30384960, 0x0 }, + { 0x30384970, 0x0 }, + { 0x30384980, 0x0 }, + { 0x30384990, 0x0 }, + { 0x303849a0, 0x0 }, + { 0x303849d0, 0x0 }, + { 0x303849e0, 0x0 }, + { 0x303849f0, 0x0 }, + { 0x303600c0, 0xd2605a56 }, + { 0x303600d0, 0xd2d2d256 }, + { 0x303600d4, 0xd2d2d256 }, + { 0x303600d8, 0xd2d2d256 }, + { 0x303600dc, 0xd2d2d256 }, + { 0x303600e0, 0x80000600 }, + { 0x303600f0, 0x101b }, + // IOMUXC (IOMUX Controller) + { 0x30330030, 0x14 }, + { 0x30330034, 0x10 }, + { 0x30330074, 0x2 }, + { 0x30330078, 0x2 }, + { 0x3033007c, 0x2 }, + { 0x30330080, 0x2 }, + { 0x30330084, 0x2 }, + { 0x30330088, 0x2 }, + { 0x3033008c, 0x2 }, + { 0x30330090, 0x2 }, + { 0x30330094, 0x2 }, + { 0x30330098, 0x2 }, + { 0x3033009c, 0x2 }, + { 0x303300a0, 0x2 }, + { 0x303300c4, 0x0 }, + { 0x30330150, 0x10 }, + { 0x30330154, 0x10 }, + { 0x30330210, 0x13 }, + { 0x30330214, 0x13 }, + { 0x3033021c, 0x1 }, + { 0x30330220, 0x1 }, + { 0x30330224, 0x1 }, + { 0x303302e4, 0x1 }, + { 0x303302e8, 0x1 }, + { 0x303302ec, 0x1 }, + { 0x303302f0, 0x1 }, + { 0x303302f4, 0x1 }, + { 0x303302f8, 0x1 }, + { 0x303302fc, 0x1 }, + { 0x30330300, 0x1 }, + { 0x30330304, 0x1 }, + { 0x30330308, 0x1 }, + { 0x3033030c, 0x1 }, + { 0x30330310, 0x1 }, + { 0x30330318, 0x59 }, + { 0x303303c0, 0x7f }, + { 0x303303c4, 0x7f }, + { 0x303303f4, 0x34 }, + { 0x303303f8, 0x59 }, + { 0x303303fc, 0x59 }, + { 0x30330400, 0x59 }, + { 0x30330404, 0x19 }, + { 0x30330408, 0x59 }, + { 0x3033040c, 0x59 }, + { 0x30330410, 0x59 }, + { 0x30330414, 0x59 }, + { 0x30330418, 0x59 }, + { 0x3033041c, 0x59 }, + { 0x30330440, 0x19 }, + { 0x30330444, 0x59 }, + { 0x30330448, 0x59 }, + { 0x3033044c, 0x59 }, + { 0x30330450, 0x59 }, + { 0x30330454, 0x59 }, + { 0x30330458, 0x59 }, + { 0x3033045c, 0x59 }, + { 0x30330460, 0x59 }, + { 0x30330464, 0x59 }, + { 0x30330468, 0x19 }, + { 0x30330480, 0x7f }, + { 0x30330484, 0x7f }, + { 0x3033048c, 0x2 }, + { 0x30330490, 0x2 }, + { 0x30330494, 0x2 }, + { 0x3033049c, 0x1 }, + { 0x303304a0, 0x1 }, + { 0x303304a4, 0x1 }, + { 0x303304a8, 0x1 }, + { 0x303304ac, 0x1 }, + { 0x303304b0, 0x1 }, + { 0x303304b4, 0x1 }, + { 0x303304b8, 0x1 }, + { 0x303304bc, 0x1 }, + { 0x303304c0, 0x1 }, + { 0x303304c4, 0x1 }, + { 0x303304c8, 0x1 }, + { 0x30330544, 0x1 }, + { 0x30330548, 0x1 }, + { 0x3033054c, 0x1 }, + { 0x303305dc, 0x1 }, + { 0x303305e0, 0x1 }, + { 0x303305ec, 0x3 }, + { 0x303305f0, 0x3 } + }; + + unsigned num_values = sizeof(initial_values) / (2*sizeof(unsigned long)); + for (unsigned i = 0; i < num_values; i++) + *((volatile unsigned long*)initial_values[i][0]) = initial_values[i][1]; + +} + + +static inline void prepare_nonsecure_world(unsigned long timer_freq) +{ + using Cpu = Hw::Arm_cpu; + + /* if we are already in HYP mode we're done (depends on u-boot version) */ + if (Cpu::Psr::M::get(Cpu::Cpsr::read()) == Cpu::Psr::M::HYP) + return; + + /* ARM generic timer counter freq needs to be set in secure mode */ + Cpu::Cntfrq::write(timer_freq); + + /* + * enable coprocessor 10 + 11 access and SMP bit access in auxiliary control + * register for non-secure world + */ + Cpu::Nsacr::access_t nsacr = 0; + Cpu::Nsacr::Cpnsae10::set(nsacr, 1); + Cpu::Nsacr::Cpnsae11::set(nsacr, 1); + Cpu::Nsacr::Ns_smp::set(nsacr, 1); + Cpu::Nsacr::write(nsacr); + + asm volatile ( + "msr sp_mon, sp \n" /* copy current mode's sp */ + "msr lr_mon, lr \n" /* copy current mode's lr */ + "cps #22 \n" /* switch to monitor mode */ + ); + + Cpu::Scr::access_t scr = 0; + Cpu::Scr::Ns::set(scr, 1); + Cpu::Scr::Fw::set(scr, 1); + Cpu::Scr::Aw::set(scr, 1); + Cpu::Scr::Scd::set(scr, 1); + Cpu::Scr::Hce::set(scr, 1); + Cpu::Scr::Sif::set(scr, 1); + Cpu::Scr::write(scr); +} + + +static inline void prepare_hypervisor(Genode::addr_t table) +{ + using Cpu = Hw::Arm_cpu; + + /* set hypervisor exception vector */ + Cpu::Hvbar::write(Hw::Mm::hypervisor_exception_vector().base); + + /* set hypervisor's translation table */ + Cpu::Httbr_64bit::write(table); + + Cpu::Ttbcr::access_t ttbcr = 0; + Cpu::Ttbcr::Irgn0::set(ttbcr, 1); + Cpu::Ttbcr::Orgn0::set(ttbcr, 1); + Cpu::Ttbcr::Sh0::set(ttbcr, 2); + Cpu::Ttbcr::Eae::set(ttbcr, 1); + + /* prepare MMU usage by hypervisor code */ + Cpu::Htcr::write(ttbcr); + + /* don't trap on cporocessor 10 + 11, but all others */ + Cpu::Hcptr::access_t hcptr = 0; + Cpu::Hcptr::Tcp<0>::set(hcptr, 1); + Cpu::Hcptr::Tcp<1>::set(hcptr, 1); + Cpu::Hcptr::Tcp<2>::set(hcptr, 1); + Cpu::Hcptr::Tcp<3>::set(hcptr, 1); + Cpu::Hcptr::Tcp<4>::set(hcptr, 1); + Cpu::Hcptr::Tcp<5>::set(hcptr, 1); + Cpu::Hcptr::Tcp<6>::set(hcptr, 1); + Cpu::Hcptr::Tcp<7>::set(hcptr, 1); + Cpu::Hcptr::Tcp<8>::set(hcptr, 1); + Cpu::Hcptr::Tcp<9>::set(hcptr, 1); + Cpu::Hcptr::Tcp<12>::set(hcptr, 1); + Cpu::Hcptr::Tcp<13>::set(hcptr, 1); + Cpu::Hcptr::Tta::set(hcptr, 1); + Cpu::Hcptr::Tcpac::set(hcptr, 1); + Cpu::Hcptr::write(hcptr); + + enum Memory_attributes { + DEVICE_MEMORY = 0x04, + NORMAL_MEMORY_UNCACHED = 0x44, + NORMAL_MEMORY_CACHED = 0xff, + }; + + Cpu::Mair0::access_t mair0 = 0; + Cpu::Mair0::Attr0::set(mair0, NORMAL_MEMORY_UNCACHED); + Cpu::Mair0::Attr1::set(mair0, DEVICE_MEMORY); + Cpu::Mair0::Attr2::set(mair0, NORMAL_MEMORY_CACHED); + Cpu::Mair0::Attr3::set(mair0, DEVICE_MEMORY); + Cpu::Hmair0::write(mair0); + + Cpu::Vtcr::access_t vtcr = ttbcr; + Cpu::Vtcr::Sl0::set(vtcr, 1); /* set to starting level 1 */ + Cpu::Vtcr::write(vtcr); + + Cpu::Sctlr::access_t sctlr = Cpu::Sctlr::read(); + Cpu::Sctlr::C::set(sctlr, 1); + Cpu::Sctlr::I::set(sctlr, 1); + Cpu::Sctlr::V::set(sctlr, 1); + Cpu::Sctlr::A::set(sctlr, 0); + Cpu::Sctlr::M::set(sctlr, 1); + Cpu::Sctlr::Z::set(sctlr, 1); + Cpu::Hsctlr::write(sctlr); +} + + +static inline void switch_to_supervisor_mode() +{ + using Cpsr = Hw::Arm_cpu::Psr; + + Cpsr::access_t cpsr = 0; + Cpsr::M::set(cpsr, Cpsr::M::SVC); + Cpsr::F::set(cpsr, 1); + Cpsr::I::set(cpsr, 1); + + asm volatile ( + "msr sp_svc, sp \n" /* copy current mode's sp */ + "msr lr_svc, lr \n" /* copy current mode's lr */ + "msr elr_hyp, lr \n" /* copy current mode's lr to hyp lr */ + "msr sp_hyp, %[stack] \n" /* copy to hyp stack pointer */ + "msr spsr_cxfs, %[cpsr] \n" /* set psr for supervisor mode */ + "adr lr, 1f \n" /* load exception return address */ + "eret \n" /* exception return */ + "1:":: [cpsr] "r" (cpsr), [stack] "r" (&hyp_mode_stack)); +} + + +unsigned Bootstrap::Platform::enable_mmu() +{ + static volatile bool primary_cpu = true; + static unsigned long timer_freq = Cpu::Cntfrq::read(); + pic.init_cpu_local(); + + prepare_nonsecure_world(timer_freq); + prepare_hypervisor((addr_t)core_pd->table_base); + switch_to_supervisor_mode(); + + Cpu::Sctlr::init(); + Cpu::Cpsr::init(); + + /* primary cpu wakes up all others */ + if (primary_cpu && NR_OF_CPUS > 1) { + cpu.invalidate_data_cache(); + primary_cpu = false; + cpu.wake_up_all_cpus(&_start_setup_stack); + } + + cpu.enable_mmu_and_caches((Genode::addr_t)core_pd->table_base); + + return Cpu::Mpidr::Aff_0::get(Cpu::Mpidr::read()); +} + + +void Bootstrap::Cpu::wake_up_all_cpus(void * const ip) +{ + struct Src : Genode::Mmio + { + struct A7_cr0 : Register<0x4, 32> + { + struct Core1_por_reset : Bitfield<1,1> {}; + struct Core1_soft_reset : Bitfield<5,1> {}; + }; + struct A7_cr1 : Register<0x8, 32> + { + struct Core1_enable : Bitfield<1,1> {}; + }; + struct Gpr3 : Register<0x7c, 32> {}; /* ep core 1 */ + struct Gpr4 : Register<0x80, 32> {}; /* ep core 1 */ + + Src(void * const entry) : Genode::Mmio(SRC_MMIO_BASE) + { + write((Gpr3::access_t)entry); + write((Gpr4::access_t)entry); + A7_cr0::access_t v0 = read(); + A7_cr0::Core1_soft_reset::set(v0,1); + write(v0); + A7_cr1::access_t v1 = read(); + A7_cr1::Core1_enable::set(v1,1); + write(v1); + } + }; + + Src src(ip); +} diff --git a/repos/base-hw/src/core/kernel/cpu.h b/repos/base-hw/src/core/kernel/cpu.h index dc6141d427..7c2fdb3d05 100644 --- a/repos/base-hw/src/core/kernel/cpu.h +++ b/repos/base-hw/src/core/kernel/cpu.h @@ -134,6 +134,8 @@ class Kernel::Cpu : public Genode::Cpu, private Irq::Pool, private Timeout Cpu(unsigned const id, Pic & pic, Inter_processor_work_list & global_work_list); + static inline unsigned primary_id() { return 0; } + /** * Raise the IPI of the CPU */ diff --git a/repos/base-hw/src/core/platform_thread.cc b/repos/base-hw/src/core/platform_thread.cc index 6c524cae65..cb553034bf 100644 --- a/repos/base-hw/src/core/platform_thread.cc +++ b/repos/base-hw/src/core/platform_thread.cc @@ -163,7 +163,7 @@ int Platform_thread::start(void * const ip, void * const sp) } unsigned const cpu = - _location.valid() ? _location.xpos() : Cpu::primary_id(); + _location.valid() ? _location.xpos() : 0; Native_utcb &utcb = *Thread::myself()->utcb(); diff --git a/repos/base-hw/src/core/spec/arm/cpu_support.h b/repos/base-hw/src/core/spec/arm/cpu_support.h index d64e6c79a1..3b74dca519 100644 --- a/repos/base-hw/src/core/spec/arm/cpu_support.h +++ b/repos/base-hw/src/core/spec/arm/cpu_support.h @@ -155,11 +155,6 @@ struct Genode::Arm_cpu : public Hw::Arm_cpu * Return kernel name of the executing CPU */ static unsigned executing_id() { return 0; } - - /** - * Return kernel name of the primary CPU - */ - static unsigned primary_id() { return 0; } }; #endif /* _CORE__SPEC__ARM__CPU_SUPPORT_H_ */ diff --git a/repos/base-hw/src/core/spec/arm_v7/virtualization/kernel/vm.cc b/repos/base-hw/src/core/spec/arm_v7/virtualization/kernel/vm.cc index 5f9599ff57..caa8c7f1f7 100644 --- a/repos/base-hw/src/core/spec/arm_v7/virtualization/kernel/vm.cc +++ b/repos/base-hw/src/core/spec/arm_v7/virtualization/kernel/vm.cc @@ -92,7 +92,7 @@ struct Kernel::Virtual_pic : Genode::Mmio Vm_irq irq { Board::VT_MAINTAINANCE_IRQ }; Virtual_pic() - : Genode::Mmio(Genode::Platform::mmio_to_virt(Board::IRQ_CONTROLLER_VT_CTRL_BASE)) { } + : Genode::Mmio(Genode::Platform::mmio_to_virt(Board::Cpu_mmio::IRQ_CONTROLLER_VT_CTRL_BASE)) { } static Virtual_pic& pic() { diff --git a/repos/base-hw/src/core/spec/arm_v7/virtualization/vm_session_component.cc b/repos/base-hw/src/core/spec/arm_v7/virtualization/vm_session_component.cc index fe53effbf7..eaf1f660a9 100644 --- a/repos/base-hw/src/core/spec/arm_v7/virtualization/vm_session_component.cc +++ b/repos/base-hw/src/core/spec/arm_v7/virtualization/vm_session_component.cc @@ -70,8 +70,8 @@ void Vm_session_component::attach(Dataspace_capability ds_cap, addr_t vm_addr) void Vm_session_component::attach_pic(addr_t vm_addr) { - _attach(Board::IRQ_CONTROLLER_VT_CPU_BASE, vm_addr, - Board::IRQ_CONTROLLER_VT_CPU_SIZE); + _attach(Board::Cpu_mmio::IRQ_CONTROLLER_VT_CPU_BASE, vm_addr, + Board::Cpu_mmio::IRQ_CONTROLLER_VT_CPU_SIZE); } diff --git a/repos/base-hw/src/core/spec/cortex_a15/cpu.h b/repos/base-hw/src/core/spec/cortex_a15/cpu.h index c4c140238e..75e329d707 100644 --- a/repos/base-hw/src/core/spec/cortex_a15/cpu.h +++ b/repos/base-hw/src/core/spec/cortex_a15/cpu.h @@ -113,10 +113,6 @@ class Genode::Cpu : public Arm_v7_cpu */ static unsigned executing_id() { return Mpidr::Aff_0::get(Mpidr::read()); } - /** - * Return kernel name of the primary CPU - */ - static unsigned primary_id(); void switch_to(Context &, Mmu_context & mmu_context) { diff --git a/repos/base-hw/src/core/spec/exynos5/cpu.cc b/repos/base-hw/src/core/spec/exynos5/cpu.cc deleted file mode 100644 index 46629a2fbf..0000000000 --- a/repos/base-hw/src/core/spec/exynos5/cpu.cc +++ /dev/null @@ -1,21 +0,0 @@ -/* - * \brief CPU driver for core - * \author Martin stein - * \author Stefan Kalkowski - * \date 2011-11-03 - */ - -/* - * Copyright (C) 2011-2017 Genode Labs GmbH - * - * This file is part of the Genode OS framework, which is distributed - * under the terms of the GNU Affero General Public License version 3. - */ - -/* core includes */ -#include -#include - -using namespace Genode; - -unsigned Cpu::primary_id() { return Board::PRIMARY_MPIDR_AFF_0; } diff --git a/repos/base-hw/src/core/spec/imx7d_sabre/board.h b/repos/base-hw/src/core/spec/imx7d_sabre/board.h new file mode 100644 index 0000000000..27ce0f36b3 --- /dev/null +++ b/repos/base-hw/src/core/spec/imx7d_sabre/board.h @@ -0,0 +1,36 @@ +/* + * \brief Board driver for core + * \author Stefan Kalkowski + * \date 2018-11-07 + */ + +/* + * Copyright (C) 2018 Genode Labs GmbH + * + * This file is part of the Genode OS framework, which is distributed + * under the terms of the GNU Affero General Public License version 3. + */ + +#ifndef _CORE__SPEC__IMX7D_SABRE__BOARD_H_ +#define _CORE__SPEC__IMX7D_SABRE__BOARD_H_ + +/* base includes */ +#include +#include + +#include + +namespace Board { + using namespace Imx7d_sabre; + using Cpu_mmio = Hw::Cortex_a15_mmio; + using Serial = Genode::Imx_uart; + + enum { + UART_BASE = UART_1_MMIO_BASE, + UART_CLOCK = 0, /* unused value */ + }; + + static constexpr bool SMP = true; +} + +#endif /* _CORE__SPEC__IMX7_SABRELITE__BOARD_H_ */ diff --git a/repos/base-hw/src/core/spec/imx7d_sabre/timer.cc b/repos/base-hw/src/core/spec/imx7d_sabre/timer.cc new file mode 100644 index 0000000000..de0b5f87ab --- /dev/null +++ b/repos/base-hw/src/core/spec/imx7d_sabre/timer.cc @@ -0,0 +1,75 @@ +/* + * \brief Timer driver for core + * \author Stefan Kalkowski + * \author Martin stein + * \date 2013-01-10 + */ + +/* + * Copyright (C) 2013-2017 Genode Labs GmbH + * + * This file is part of the Genode OS framework, which is distributed + * under the terms of the GNU Affero General Public License version 3. + */ + +#include +#include +#include +#include + +using namespace Genode; +using namespace Kernel; + + +unsigned Timer::interrupt_id() const +{ + return 30; +} + +unsigned long Timer_driver::_freq() +{ + unsigned long freq; + asm volatile("mrc p15, 0, %0, c14, c0, 0\n" : "=r" (freq)); + return freq; +} + + +Timer_driver::Timer_driver(unsigned) : ticks_per_ms(_freq() / 1000) +{ + unsigned long ctrl; + asm volatile("mrc p15, 0, %0, c14, c2, 1\n" : "=r" (ctrl)); + asm volatile("mcr p15, 0, %0, c14, c2, 1\n" :: "r" (ctrl | 1)); +} + + +void Timer::_start_one_shot(time_t const ticks) +{ + unsigned long ctrl; + unsigned long v0, v1; + asm volatile("mrrc p15, 0, %0, %1, c14\n" : "=r" (v0), "=r" (v1)); + _driver.last_time = (Genode::uint64_t)v0 | (Genode::uint64_t)v1 << 32; + asm volatile("mcr p15, 0, %0, c14, c2, 0\n" :: "r" (ticks)); + asm volatile("mrc p15, 0, %0, c14, c2, 1\n" : "=r" (ctrl)); + asm volatile("mcr p15, 0, %0, c14, c2, 1\n" :: "r" (ctrl & ~4UL)); +} + + +time_t Timer::_duration() const +{ + unsigned long v0, v1; + asm volatile("mrrc p15, 0, %0, %1, c14\n" : "=r" (v0), "=r" (v1)); + Genode::uint64_t v = (Genode::uint64_t)v0 | (Genode::uint64_t)v1 << 32; + return v - _driver.last_time; +} + + +time_t Timer::ticks_to_us(time_t const ticks) const { + return timer_ticks_to_us(ticks, _driver.ticks_per_ms); } + + +time_t Timer::us_to_ticks(time_t const us) const { + return (us / 1000) * _driver.ticks_per_ms; } + + +time_t Timer::_max_value() const { + return _driver.ticks_per_ms * 5000; } diff --git a/repos/base-hw/src/core/spec/imx7d_sabre/timer_driver.h b/repos/base-hw/src/core/spec/imx7d_sabre/timer_driver.h new file mode 100644 index 0000000000..b6d911036f --- /dev/null +++ b/repos/base-hw/src/core/spec/imx7d_sabre/timer_driver.h @@ -0,0 +1,34 @@ +/* + * \brief Timer driver for core + * \author Martin stein + * \date 2013-01-10 + */ + +/* + * Copyright (C) 2013-2017 Genode Labs GmbH + * + * This file is part of the Kernel OS framework, which is distributed + * under the terms of the GNU Affero General Public License version 3. + */ + +#ifndef _TIMER_DRIVER_H_ +#define _TIMER_DRIVER_H_ + +/* base-hw includes */ +#include + +namespace Kernel { class Timer_driver; } + + +struct Kernel::Timer_driver +{ + unsigned long _freq(); + + unsigned const ticks_per_ms; + + time_t last_time { 0 }; + + Timer_driver(unsigned); +}; + +#endif /* _TIMER_DRIVER_H_ */ diff --git a/repos/base-hw/src/core/spec/riscv/cpu.h b/repos/base-hw/src/core/spec/riscv/cpu.h index 49c1daea04..98691a3c69 100644 --- a/repos/base-hw/src/core/spec/riscv/cpu.h +++ b/repos/base-hw/src/core/spec/riscv/cpu.h @@ -81,7 +81,6 @@ class Genode::Cpu : public Hw::Riscv_cpu static void mmu_fault(Context & c, Kernel::Thread_fault & f); static unsigned executing_id() { return 0; } - static unsigned primary_id() { return 0; } }; #endif /* _CORE__SPEC__RISCV__CPU_H_ */ diff --git a/repos/base-hw/src/core/spec/x86_64/cpu.h b/repos/base-hw/src/core/spec/x86_64/cpu.h index 051ab6e59a..f88a5df9ed 100644 --- a/repos/base-hw/src/core/spec/x86_64/cpu.h +++ b/repos/base-hw/src/core/spec/x86_64/cpu.h @@ -121,11 +121,6 @@ class Genode::Cpu : public Hw::X86_64_cpu */ static unsigned executing_id(); - /** - * Return kernel name of the primary CPU - */ - static unsigned primary_id() { return 0; } - /** * Switch to new context * diff --git a/repos/base-hw/src/lib/hw/spec/arm/cortex_a15.h b/repos/base-hw/src/lib/hw/spec/arm/cortex_a15.h index c24122c0de..a7db5127e6 100644 --- a/repos/base-hw/src/lib/hw/spec/arm/cortex_a15.h +++ b/repos/base-hw/src/lib/hw/spec/arm/cortex_a15.h @@ -22,10 +22,13 @@ template struct Hw::Cortex_a15_mmio { enum { - IRQ_CONTROLLER_DISTR_BASE = BASE + 0x1000, - IRQ_CONTROLLER_DISTR_SIZE = 0x1000, - IRQ_CONTROLLER_CPU_BASE = BASE + 0x2000, - IRQ_CONTROLLER_CPU_SIZE = 0x2000, + IRQ_CONTROLLER_DISTR_BASE = BASE + 0x1000UL, + IRQ_CONTROLLER_DISTR_SIZE = 0x1000UL, + IRQ_CONTROLLER_CPU_BASE = BASE + 0x2000UL, + IRQ_CONTROLLER_CPU_SIZE = 0x2000UL, + IRQ_CONTROLLER_VT_CTRL_BASE = BASE + 0x4000UL, + IRQ_CONTROLLER_VT_CPU_BASE = BASE + 0x6000UL, + IRQ_CONTROLLER_VT_CPU_SIZE = 0x1000UL, }; }; diff --git a/repos/base/include/drivers/defs/exynos5.h b/repos/base/include/drivers/defs/exynos5.h index 0a4986e7b2..84b6e6c957 100644 --- a/repos/base/include/drivers/defs/exynos5.h +++ b/repos/base/include/drivers/defs/exynos5.h @@ -60,9 +60,6 @@ namespace Exynos5 { /* IRAM */ IRAM_BASE = 0x02020000, - /* hardware name of the primary processor */ - PRIMARY_MPIDR_AFF_0 = 0, - /* SATA/AHCI */ SATA_IRQ = 147, diff --git a/repos/base/include/drivers/defs/imx7d_sabre.h b/repos/base/include/drivers/defs/imx7d_sabre.h new file mode 100644 index 0000000000..df1e0e1a85 --- /dev/null +++ b/repos/base/include/drivers/defs/imx7d_sabre.h @@ -0,0 +1,44 @@ +/* + * \brief Definitions for the Imx7 dual sabre board + * \author Stefan Kalkowski + * \date 2018-10-07 + */ + +/* + * Copyright (C) 2018 Genode Labs GmbH + * + * This file is part of the Genode OS framework, which is distributed + * under the terms of the GNU Affero General Public License version 3. + */ + +#ifndef _INCLUDE__DRIVERS__DEFS__IMX7D_SABRE_H_ +#define _INCLUDE__DRIVERS__DEFS__IMX7D_SABRE_H_ + +namespace Imx7d_sabre { + + enum { + RAM_0_BASE = 0x80000000UL, + RAM_0_SIZE = 0x40000000UL, + + IRQ_CONTROLLER_BASE = 0x31000000UL, + IRQ_CONTROLLER_SIZE = 0x8000, + + SRC_MMIO_BASE = 0x30390000UL, + + AIPS_1_MMIO_BASE = 0x301f0000UL, + AIPS_2_MMIO_BASE = 0x305f0000UL, + AIPS_3_MMIO_BASE = 0x309f0000UL, + + UART_1_MMIO_BASE = 0x30860000UL, + UART_1_MMIO_SIZE = 0x10000UL, + + TIMER_CLOCK = 1000000000UL, + + CACHE_LINE_SIZE_LOG2 = 6, + + VT_MAINTAINANCE_IRQ, + VT_TIMER_IRQ, + }; +} + +#endif /* _INCLUDE__DRIVERS__DEFS__IMX7D_SABRE_H_ */ diff --git a/tool/run/boot_dir/hw b/tool/run/boot_dir/hw index 45d3aa7a7d..2b4b328ada 100644 --- a/tool/run/boot_dir/hw +++ b/tool/run/boot_dir/hw @@ -13,6 +13,7 @@ proc bootstrap_link_address { } { if {[have_spec "wand_quad"]} { return "0x10001000" } if {[have_spec "imx6q_sabrelite"]} { return "0x10001000" } if {[have_spec "imx53_qsb"]} { return "0x70010000" } + if {[have_spec "imx7d_sabre"]} { return "0x88000000" } if {[have_spec "arndale"]} { return "0x88000000" } if {[have_spec "panda"]} { return "0x88000000" } if {[have_spec "zynq"]} { return "0x00100000" }