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AVL node/tree: make non-copyable

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AVL trees can't be copied with the default copy constructor as the
parent pointer of the first item of both of the resulting trees would
point to the original tree. Copying an AVL node, however, generally
violates the integrity of the corresponding tree. The copy constructor
of Avl_tree is used in some places but in those places it can be
replaced easily. So, this commit deletes the copy constructor of
Avl_node_base which makes Avl_node and Avl_tree non-copyable.

Issue #2654
This commit is contained in:
Martin Stein 2018-01-24 14:02:35 +01:00 committed by Norman Feske
parent 4e9ff5ad7b
commit abf9557bb5
13 changed files with 84 additions and 55 deletions
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2
repos/base-foc/src/core/platform.cc
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@ -416,7 +416,7 @@ Platform::Platform() :
_ram_alloc(nullptr), _io_mem_alloc(core_mem_alloc()),
_io_port_alloc(core_mem_alloc()), _irq_alloc(core_mem_alloc()),
_region_alloc(core_mem_alloc()), _cap_id_alloc(core_mem_alloc()),
_kip_rom(Rom_module((addr_t)sigma0_map_kip(), L4_PAGESIZE, "l4v2_kip")),
_kip_rom((addr_t)sigma0_map_kip(), L4_PAGESIZE, "l4v2_kip"),
_sigma0(cap_map()->insert(_cap_id_alloc.alloc(), Fiasco::L4_BASE_PAGER_CAP))
{
/*

2
repos/base-foc/src/include/base/internal/capability_data.h
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@ -26,7 +26,7 @@
* (platform-specific) capability space of the component. Therefore it
* shouldn't be copied around, but only referenced by e.g. Native_capability.
*/
class Genode::Native_capability::Data : public Avl_node<Data>, Noncopyable
class Genode::Native_capability::Data : public Avl_node<Data>
{
private:

4
repos/base-hw/src/core/spec/arm_v7/virtualization/kernel/vm.cc
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@ -88,7 +88,7 @@ struct Kernel::Virtual_pic : Genode::Mmio
template <unsigned SLOT>
struct Gich_lr : Register<0x100 + SLOT*4, 32> { };
Vm_irq irq = Board::VT_MAINTAINANCE_IRQ;
Vm_irq irq { Board::VT_MAINTAINANCE_IRQ };
Virtual_pic()
: Genode::Mmio(Genode::Platform::mmio_to_virt(Board::IRQ_CONTROLLER_VT_CTRL_BASE)) { }
@ -139,7 +139,7 @@ struct Kernel::Virtual_pic : Genode::Mmio
struct Kernel::Virtual_timer
{
Vm_irq irq = Board::VT_TIMER_IRQ;
Vm_irq irq { Board::VT_TIMER_IRQ };
/**
* Return virtual timer object of currently executing cpu

3
repos/base-nova/src/core/platform.cc
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@ -20,6 +20,7 @@
#include <util/string.h>
#include <util/xml_generator.h>
#include <trace/source_registry.h>
#include <util/construct_at.h>
/* core includes */
#include <boot_modules.h>
@ -737,7 +738,7 @@ Platform::Platform() :
addr_t core_local_addr = _map_pages(phys_addr, 1);
Cap_range * range = reinterpret_cast<Cap_range *>(core_local_addr);
*range = Cap_range(index);
construct_at<Cap_range>(range, index);
cap_map()->insert(range);

2
repos/base-nova/src/lib/base/stack.cc
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@ -91,7 +91,7 @@ void prepare_init_main_thread()
for (unsigned i = 0; i < CAP_RANGES; i++) {
Cap_range * range = reinterpret_cast<Cap_range *>(local[i]);
*range = Cap_range(index);
construct_at<Cap_range>(range, index);
cap_map()->insert(range);

3
repos/base-nova/src/test/platform/main.cc
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@ -662,8 +662,7 @@ Main::Main(Env &env) : env(env)
static char local[128][sizeof(Cap_range)];
for (unsigned i = 0; i < sizeof(local) / sizeof (local[0]); i++) {
Cap_range * range = reinterpret_cast<Cap_range *>(local[i]);
*range = Cap_range(index);
Cap_range * range = construct_at<Cap_range>(local[i], index);
cap_map()->insert(range);

5
repos/base-sel4/src/include/base/internal/capability_space_sel4.h
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@ -17,6 +17,7 @@
/* base includes */
#include <util/avl_tree.h>
#include <base/lock.h>
#include <util/construct_at.h>
/* base-internal includes */
#include <base/internal/capability_space.h>
@ -193,7 +194,7 @@ class Genode::Capability_space_sel4
if (_caps_data[_index(data)].rpc_obj_key().valid())
_tree.remove(static_cast<Tree_managed_data *>(&data));
_caps_data[_index(data)] = Tree_managed_data();
construct_at<Tree_managed_data>(&_caps_data[_index(data)]);
}
public:
@ -218,7 +219,7 @@ class Genode::Capability_space_sel4
Lock::Guard guard(_lock);
_caps_data[sel] = Tree_managed_data(args...);
construct_at<Tree_managed_data>(&_caps_data[sel], args...);
if (_caps_data[sel].rpc_obj_key().valid())
_tree.insert(&_caps_data[sel]);

2
repos/base/include/base/id_space.h
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@ -39,7 +39,7 @@ class Genode::Id_space : public Noncopyable
class Out_of_ids : Exception { };
class Conflicting_id : Exception { };
class Element : public Avl_node<Element>, Noncopyable
class Element : public Avl_node<Element>
{
private:

2
repos/base/include/util/avl_string.h
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@ -28,7 +28,7 @@ class Genode::Avl_string_base : public Avl_node<Avl_string_base>
{
private:
const char *_str;
struct { const char *_str; };
protected:

11
repos/base/include/util/avl_tree.h
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@ -15,6 +15,7 @@
#define _INCLUDE__UTIL__AVL_TREE_H_
#include <util/misc_math.h>
#include <util/noncopyable.h>
namespace Genode {
@ -24,7 +25,7 @@ namespace Genode {
}
class Genode::Avl_node_base
class Genode::Avl_node_base : Noncopyable
{
protected:
@ -58,9 +59,11 @@ class Genode::Avl_node_base
virtual void recompute(Avl_node_base *) { }
};
Avl_node_base *_child[2]; /* left and right subtrees */
Avl_node_base *_parent; /* parent of subtree */
unsigned char _depth; /* depth of subtree */
struct {
Avl_node_base *_child[2]; /* left and right subtrees */
Avl_node_base *_parent; /* parent of subtree */
unsigned char _depth; /* depth of subtree */
};
public:

3
repos/base/src/include/base/internal/capability_space_tpl.h
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@ -25,6 +25,7 @@
#include <util/bit_allocator.h>
#include <base/lock.h>
#include <base/log.h>
#include <util/construct_at.h>
/* base-internal includes */
#include <base/internal/capability_space.h>
@ -149,7 +150,7 @@ class Genode::Capability_space_tpl
addr_t const index = _alloc.alloc();
_caps_data[index] = Tree_managed_data(args...);
construct_at<Tree_managed_data>(&_caps_data[index], args...);
if (_caps_data[index].rpc_obj_key().valid())
_tree.insert(&_caps_data[index]);

6
repos/os/src/server/nic_router/dhcp_server.h
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@ -83,8 +83,7 @@ class Net::Dhcp_server : private Genode::Noncopyable
};
struct Net::Dhcp_allocation_tree : public Genode::Avl_tree<Dhcp_allocation>,
private Genode::Noncopyable
struct Net::Dhcp_allocation_tree : public Genode::Avl_tree<Dhcp_allocation>
{
struct No_match : Genode::Exception { };
@ -93,8 +92,7 @@ struct Net::Dhcp_allocation_tree : public Genode::Avl_tree<Dhcp_allocation>,
class Net::Dhcp_allocation : public Genode::Avl_node<Dhcp_allocation>,
public Dhcp_allocation_list::Element,
private Genode::Noncopyable
public Dhcp_allocation_list::Element
{
protected:

94
repos/os/src/server/vmm/main.cc
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@ -429,45 +429,71 @@ class Vmm
{
private:
Register _regs[27] {
{ 0, 0, 0, 0, "MIDR", false, &State::midr, 0x412fc0f1 },
{ 0, 0, 0, 5, "MPIDR", false, &State::mpidr, 0x40000000 },
{ 0, 0, 0, 1, "CTR", false, &State::ctr, 0x8444c004 },
{ 0, 1, 0, 0, "CCSIDR", false, &State::ccsidr, 0x701fe00a },
{ 0, 1, 0, 1, "CLIDR", false, &State::clidr, 0x0a200023 },
{ 0, 0, 1, 0, "PFR0", false, &State::pfr0, 0x00001031 },
{ 0, 0, 1, 4, "MMFR0", false, &State::mmfr0, 0x10201105 },
{ 0, 0, 2, 0, "ISAR0", false, &State::isar0, 0x02101110 },
{ 0, 0, 2, 3, "ISAR3", false, &State::isar3, 0x11112131 },
{ 0, 0, 2, 4, "ISAR4", false, &State::isar4, 0x10011142 },
{ 0, 2, 0, 0, "CSSELR", true, &State::csselr, 0x00000000 },
{ 1, 0, 0, 0, "SCTRL", true, &State::sctrl, 0 /* 0xc5007a 0x00c5187a*/ },
{ 1, 0, 0, 1, "ACTRL", true, &State::actrl, 0x00000040 },
{ 1, 0, 0, 2, "CPACR", true, &State::cpacr, 0x00000000 },
{ 2, 0, 0, 0, "TTBR0", true, &State::ttbr0, 0x00000000 },
{ 2, 0, 0, 1, "TTBR1", true, &State::ttbr1, 0x00000000 },
{ 2, 0, 0, 2, "TTBCR", true, &State::ttbcr, 0x00000000 },
{ 3, 0, 0, 0, "DACR", true, &State::dacr, 0x55555555 },
{ 5, 0, 0, 0, "DFSR", true, &State::dfsr, 0x00000000 },
{ 5, 0, 0, 1, "IFSR", true, &State::ifsr, 0x00000000 },
{ 5, 0, 1, 0, "ADFSR", true, &State::adfsr, 0x00000000 },
{ 5, 0, 1, 1, "AIFSR", true, &State::aifsr, 0x00000000 },
{ 6, 0, 0, 0, "DFAR", true, &State::dfar, 0x00000000 },
{ 6, 0, 0, 2, "IFAR", true, &State::ifar, 0x00000000 },
{ 10, 0, 2, 0, "PRRR", true, &State::prrr, 0x00098aa4 },
{ 10, 0, 2, 1, "NMRR", true, &State::nmrr, 0x44e048e0 },
{ 13, 0, 0, 1, "CONTEXTIDR", true, &State::cidr, 0x00000000 }
};
Register _regs_0 { 0, 0, 0, 0, "MIDR", false, &State::midr, 0x412fc0f1 };
Register _regs_1 { 0, 0, 0, 5, "MPIDR", false, &State::mpidr, 0x40000000 };
Register _regs_2 { 0, 0, 0, 1, "CTR", false, &State::ctr, 0x8444c004 };
Register _regs_3 { 0, 1, 0, 0, "CCSIDR", false, &State::ccsidr, 0x701fe00a };
Register _regs_4 { 0, 1, 0, 1, "CLIDR", false, &State::clidr, 0x0a200023 };
Register _regs_5 { 0, 0, 1, 0, "PFR0", false, &State::pfr0, 0x00001031 };
Register _regs_6 { 0, 0, 1, 4, "MMFR0", false, &State::mmfr0, 0x10201105 };
Register _regs_7 { 0, 0, 2, 0, "ISAR0", false, &State::isar0, 0x02101110 };
Register _regs_8 { 0, 0, 2, 3, "ISAR3", false, &State::isar3, 0x11112131 };
Register _regs_9 { 0, 0, 2, 4, "ISAR4", false, &State::isar4, 0x10011142 };
Register _regs_10 { 0, 2, 0, 0, "CSSELR", true, &State::csselr, 0x00000000 };
Register _regs_11 { 1, 0, 0, 0, "SCTRL", true, &State::sctrl, 0 /* 0xc5007a 0x00c5187a*/ };
Register _regs_12 { 1, 0, 0, 1, "ACTRL", true, &State::actrl, 0x00000040 };
Register _regs_13 { 1, 0, 0, 2, "CPACR", true, &State::cpacr, 0x00000000 };
Register _regs_14 { 2, 0, 0, 0, "TTBR0", true, &State::ttbr0, 0x00000000 };
Register _regs_15 { 2, 0, 0, 1, "TTBR1", true, &State::ttbr1, 0x00000000 };
Register _regs_16 { 2, 0, 0, 2, "TTBCR", true, &State::ttbcr, 0x00000000 };
Register _regs_17 { 3, 0, 0, 0, "DACR", true, &State::dacr, 0x55555555 };
Register _regs_18 { 5, 0, 0, 0, "DFSR", true, &State::dfsr, 0x00000000 };
Register _regs_19 { 5, 0, 0, 1, "IFSR", true, &State::ifsr, 0x00000000 };
Register _regs_20 { 5, 0, 1, 0, "ADFSR", true, &State::adfsr, 0x00000000 };
Register _regs_21 { 5, 0, 1, 1, "AIFSR", true, &State::aifsr, 0x00000000 };
Register _regs_22 { 6, 0, 0, 0, "DFAR", true, &State::dfar, 0x00000000 };
Register _regs_23 { 6, 0, 0, 2, "IFAR", true, &State::ifar, 0x00000000 };
Register _regs_24 { 10, 0, 2, 0, "PRRR", true, &State::prrr, 0x00098aa4 };
Register _regs_25 { 10, 0, 2, 1, "NMRR", true, &State::nmrr, 0x44e048e0 };
Register _regs_26 { 13, 0, 0, 1, "CONTEXTIDR", true, &State::cidr, 0x00000000 };
void _init_reg(Register &reg, State &state)
{
_reg_tree.insert(&reg);
reg.write(state, reg.init_value());
}
public:
Cp15(State & state)
{
for (unsigned i = 0; i < (sizeof(_regs) / sizeof(Register));
i++) {
_reg_tree.insert(&_regs[i]);
_regs[i].write(state, _regs[i].init_value());
}
_init_reg(_regs_0, state);
_init_reg(_regs_1, state);
_init_reg(_regs_2, state);
_init_reg(_regs_3, state);
_init_reg(_regs_4, state);
_init_reg(_regs_5, state);
_init_reg(_regs_6, state);
_init_reg(_regs_7, state);
_init_reg(_regs_8, state);
_init_reg(_regs_9, state);
_init_reg(_regs_10, state);
_init_reg(_regs_11, state);
_init_reg(_regs_12, state);
_init_reg(_regs_13, state);
_init_reg(_regs_14, state);
_init_reg(_regs_15, state);
_init_reg(_regs_16, state);
_init_reg(_regs_17, state);
_init_reg(_regs_18, state);
_init_reg(_regs_19, state);
_init_reg(_regs_20, state);
_init_reg(_regs_21, state);
_init_reg(_regs_22, state);
_init_reg(_regs_23, state);
_init_reg(_regs_24, state);
_init_reg(_regs_25, state);
_init_reg(_regs_26, state);
}
};