ExternalVendorCode/genode
1
0
Fork 0
mirror of https://github.com/genodelabs/genode.git synced 2024-12-23 15:32:25 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

platform_drv: add UHCI PCI quirks

Browse Source 
Implement BIOS handover and Intel resume register update
apart from device driver to circumvent export of PCI
config space to drivers.

Ref genodelabs/genode#4578
This commit is contained in:
Stefan Kalkowski 2022-07-25 15:11:31 +02:00 committed by Christian Helmuth
parent 413e2baa1c
commit 9dfc2caa11
2 changed files with 68 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
repos/os/src/drivers/platform/pci.cc
View File

@ -18,10 +18,12 @@
#include <device.h>
#include <device_pd.h>
#include <pci.h>
#include <pci_uhci.h>
using namespace Genode;
using namespace Pci;
struct Config_helper
{
Driver::Device const & _dev;
@ -56,6 +58,9 @@ struct Config_helper
Config::Command::Io_space_enable::set(cmd, 1); });
_config.write<Config::Command>(cmd);
/* apply different PCI quirks, bios handover etc. */
Driver::pci_uhci_quirks(_cfg, _config.base());
}
void disable()

63
repos/os/src/drivers/platform/pci_uhci.h Normal file
View File

@ -0,0 +1,63 @@
/*
* \brief Platform driver - PCI UHCI utilities
* \author Stefan Kalkowski
* \date 2022-06-02
*/
/*
* Copyright (C) 2022 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#include <pci/config.h>
#include <device.h>
namespace Driver {
static void pci_uhci_quirks(Device::Pci_config cfg, addr_t base);
}
void Driver::pci_uhci_quirks(Device::Pci_config cfg, addr_t base)
{
enum { UHCI_CLASS_CODE = 0xc0300 };
if (cfg.class_code != UHCI_CLASS_CODE)
return;
/* PCI configuration register for UHCI */
struct Uhci : Mmio
{
struct Usb_legacy_support : Register<0xc0, 16>
{
struct Trap_by_60h_read_status : Bitfield<8, 1> {};
struct Trap_by_60h_write_status : Bitfield<9, 1> {};
struct Trap_by_64h_read_status : Bitfield<10,1> {};
struct Trap_by_64h_write_status : Bitfield<11,1> {};
struct Usb_pirq_enable : Bitfield<13,1> {};
struct End_of_a20gate_pass_through_status : Bitfield<15,1> {};
};
struct Usb_resume_intel : Register<0xc4, 16> {};
using Mmio::Mmio;
};
Uhci config(base);
using Reg = Uhci::Usb_legacy_support;
/* BIOS handover */
Reg::access_t reg = 0;
Reg::Trap_by_60h_read_status::set(reg,1);
Reg::Trap_by_60h_write_status::set(reg,1);
Reg::Trap_by_64h_read_status::set(reg,1);
Reg::Trap_by_64h_write_status::set(reg,1);
Reg::End_of_a20gate_pass_through_status::set(reg,1);
Reg::Usb_pirq_enable::set(reg,1);
config.write<Reg>(reg);
if (cfg.vendor_id == 0x8086)
config.write<Uhci::Usb_resume_intel>(0);
}