From 9dfc2caa111aef58e2d47d0a364e9dcda80c1aae Mon Sep 17 00:00:00 2001
From: Stefan Kalkowski <stefan.kalkowski@genode-labs.com>
Date: Mon, 25 Jul 2022 15:11:31 +0200
Subject: [PATCH] platform_drv: add UHCI PCI quirks

Implement BIOS handover and Intel resume register update
apart from device driver to circumvent export of PCI
config space to drivers.

Ref genodelabs/genode#4578
---
 repos/os/src/drivers/platform/pci.cc     |  5 ++
 repos/os/src/drivers/platform/pci_uhci.h | 63 ++++++++++++++++++++++++
 2 files changed, 68 insertions(+)
 create mode 100644 repos/os/src/drivers/platform/pci_uhci.h

diff --git a/repos/os/src/drivers/platform/pci.cc b/repos/os/src/drivers/platform/pci.cc
index 4f2bc08350..d37d9bab4f 100644
--- a/repos/os/src/drivers/platform/pci.cc
+++ b/repos/os/src/drivers/platform/pci.cc
@@ -18,10 +18,12 @@
 #include <device.h>
 #include <device_pd.h>
 #include <pci.h>
+#include <pci_uhci.h>
 
 using namespace Genode;
 using namespace Pci;
 
+
 struct Config_helper
 {
 	Driver::Device             const & _dev;
@@ -56,6 +58,9 @@ struct Config_helper
 				Config::Command::Io_space_enable::set(cmd, 1); });
 
 		_config.write<Config::Command>(cmd);
+
+		/* apply different PCI quirks, bios handover etc. */
+		Driver::pci_uhci_quirks(_cfg, _config.base());
 	}
 
 	void disable()
diff --git a/repos/os/src/drivers/platform/pci_uhci.h b/repos/os/src/drivers/platform/pci_uhci.h
new file mode 100644
index 0000000000..9d52a9bdd5
--- /dev/null
+++ b/repos/os/src/drivers/platform/pci_uhci.h
@@ -0,0 +1,63 @@
+/*
+ * \brief  Platform driver - PCI UHCI utilities
+ * \author Stefan Kalkowski
+ * \date   2022-06-02
+ */
+
+/*
+ * Copyright (C) 2022 Genode Labs GmbH
+ *
+ * This file is part of the Genode OS framework, which is distributed
+ * under the terms of the GNU Affero General Public License version 3.
+ */
+
+#include <pci/config.h>
+#include <device.h>
+
+namespace Driver {
+	static void pci_uhci_quirks(Device::Pci_config cfg, addr_t base);
+}
+
+
+void Driver::pci_uhci_quirks(Device::Pci_config cfg, addr_t base)
+{
+	enum { UHCI_CLASS_CODE = 0xc0300 };
+
+	if (cfg.class_code != UHCI_CLASS_CODE)
+		return;
+
+	/* PCI configuration register for UHCI */
+	struct Uhci : Mmio
+	{
+		struct Usb_legacy_support : Register<0xc0, 16>
+		{
+			struct Trap_by_60h_read_status            : Bitfield<8, 1> {};
+			struct Trap_by_60h_write_status           : Bitfield<9, 1> {};
+			struct Trap_by_64h_read_status            : Bitfield<10,1> {};
+			struct Trap_by_64h_write_status           : Bitfield<11,1> {};
+			struct Usb_pirq_enable                    : Bitfield<13,1> {};
+			struct End_of_a20gate_pass_through_status : Bitfield<15,1> {};
+		};
+
+		struct Usb_resume_intel : Register<0xc4, 16> {};
+
+		using Mmio::Mmio;
+	};
+
+	Uhci config(base);
+
+	using Reg = Uhci::Usb_legacy_support;
+
+	/* BIOS handover */
+	Reg::access_t reg = 0;
+	Reg::Trap_by_60h_read_status::set(reg,1);
+	Reg::Trap_by_60h_write_status::set(reg,1);
+	Reg::Trap_by_64h_read_status::set(reg,1);
+	Reg::Trap_by_64h_write_status::set(reg,1);
+	Reg::End_of_a20gate_pass_through_status::set(reg,1);
+	Reg::Usb_pirq_enable::set(reg,1);
+	config.write<Reg>(reg);
+
+	if (cfg.vendor_id == 0x8086)
+		config.write<Uhci::Usb_resume_intel>(0);
+}