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pci_decode: export prefetchable attribute of BARs
Memory descriptors in PCI BARs have a prefetchable bit, which can be used to optimize memory access when setting, e.g. write-combined in page-table entries. Ref genodelabs/genode#4578
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@ -96,6 +96,8 @@ struct Pci::Config : Genode::Mmio
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enum { SIZE_32BIT = 0, SIZE_64BIT = 2 };
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};
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struct Memory_prefetchable : Bitfield<3,1> {};
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struct Io_base : Bitfield<2, 30> {};
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struct Memory_base : Bitfield<7, 25> {};
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};
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@ -123,6 +125,9 @@ struct Pci::Config : Genode::Mmio
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Bar_32bit::Memory_type::SIZE_64BIT;
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}
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bool prefetchable() {
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return Bar_32bit::Memory_prefetchable::get(_conf); }
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Genode::size_t size()
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{
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return 1 + (memory() ? ~Bar_32bit::Memory_base::masked(_conf)
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@ -524,7 +529,7 @@ struct Pci::Config : Genode::Mmio
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if (!reg0.valid())
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continue;
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if (reg0.memory()) {
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memory(reg0.addr(), reg0.size(), i);
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memory(reg0.addr(), reg0.size(), i, reg0.prefetchable());
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if (reg0.bit64()) i++;
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} else
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io(reg0.addr(), reg0.size(), i);
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@ -126,12 +126,15 @@ void Main::parse_pci_function(Bdf bdf,
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}
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});
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cfg.for_each_bar([&] (uint64_t addr, size_t size, unsigned bar) {
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cfg.for_each_bar([&] (uint64_t addr, size_t size,
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unsigned bar, bool pf)
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{
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gen.node("io_mem", [&]
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{
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gen.attribute("pci_bar", bar);
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gen.attribute("address", string(addr));
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gen.attribute("size", string(size));
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if (pf) gen.attribute("prefetchable", true);
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});
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}, [&] (uint64_t addr, size_t size, unsigned bar) {
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gen.node("io_port_range", [&]
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