From 7334128a2eaf880454b58b733de1c8db07fd52e6 Mon Sep 17 00:00:00 2001 From: Stefan Kalkowski Date: Wed, 28 Sep 2022 13:56:17 +0200 Subject: [PATCH] pci_decode: export prefetchable attribute of BARs Memory descriptors in PCI BARs have a prefetchable bit, which can be used to optimize memory access when setting, e.g. write-combined in page-table entries. Ref genodelabs/genode#4578 --- repos/os/include/pci/config.h | 7 ++++++- repos/os/src/app/pci_decode/main.cc | 5 ++++- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/repos/os/include/pci/config.h b/repos/os/include/pci/config.h index f96f25e10e..430093af07 100644 --- a/repos/os/include/pci/config.h +++ b/repos/os/include/pci/config.h @@ -96,6 +96,8 @@ struct Pci::Config : Genode::Mmio enum { SIZE_32BIT = 0, SIZE_64BIT = 2 }; }; + struct Memory_prefetchable : Bitfield<3,1> {}; + struct Io_base : Bitfield<2, 30> {}; struct Memory_base : Bitfield<7, 25> {}; }; @@ -123,6 +125,9 @@ struct Pci::Config : Genode::Mmio Bar_32bit::Memory_type::SIZE_64BIT; } + bool prefetchable() { + return Bar_32bit::Memory_prefetchable::get(_conf); } + Genode::size_t size() { return 1 + (memory() ? ~Bar_32bit::Memory_base::masked(_conf) @@ -524,7 +529,7 @@ struct Pci::Config : Genode::Mmio if (!reg0.valid()) continue; if (reg0.memory()) { - memory(reg0.addr(), reg0.size(), i); + memory(reg0.addr(), reg0.size(), i, reg0.prefetchable()); if (reg0.bit64()) i++; } else io(reg0.addr(), reg0.size(), i); diff --git a/repos/os/src/app/pci_decode/main.cc b/repos/os/src/app/pci_decode/main.cc index a86e05edb1..8a08b611c3 100644 --- a/repos/os/src/app/pci_decode/main.cc +++ b/repos/os/src/app/pci_decode/main.cc @@ -126,12 +126,15 @@ void Main::parse_pci_function(Bdf bdf, } }); - cfg.for_each_bar([&] (uint64_t addr, size_t size, unsigned bar) { + cfg.for_each_bar([&] (uint64_t addr, size_t size, + unsigned bar, bool pf) + { gen.node("io_mem", [&] { gen.attribute("pci_bar", bar); gen.attribute("address", string(addr)); gen.attribute("size", string(size)); + if (pf) gen.attribute("prefetchable", true); }); }, [&] (uint64_t addr, size_t size, unsigned bar) { gen.node("io_port_range", [&]