ExternalVendorCode/genode
1
0
Fork 0
mirror of https://github.com/genodelabs/genode.git synced 2025-01-18 18:56:29 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

hw: add TrustZone support for i.MX53 (ref #954)

Browse Source
This commit is contained in:
Stefan Kalkowski 2013-11-18 13:03:12 +01:00 committed by Norman Feske
parent 238430a362
commit 6f136bef7a
16 changed files with 685 additions and 37 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

33
base-hw/include/platform/imx53/drivers/trustzone.h Normal file
View File

@ -0,0 +1,33 @@
/*
* \brief TrustZone specific definitions for the i.MX53 board
* \author Stefan Kalkowski
* \date 2013-11-15
*/
/*
* Copyright (C) 2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__PLATFORM__IMX53__DRIVERS__TRUSTZONE_H_
#define _INCLUDE__PLATFORM__IMX53__DRIVERS__TRUSTZONE_H_
/* Genode includes */
#include <drivers/board_base.h>
namespace Trustzone
{
enum {
VM_STATE_SIZE = 1 << 20,
SECURE_RAM_BASE = Genode::Board_base::RAM0_BASE,
SECURE_RAM_SIZE = Genode::Board_base::RAM0_SIZE - VM_STATE_SIZE,
VM_STATE_BASE = SECURE_RAM_BASE + SECURE_RAM_SIZE,
NONSECURE_RAM_BASE = Genode::Board_base::RAM1_BASE,
NONSECURE_RAM_SIZE = Genode::Board_base::RAM1_SIZE,
};
}
#endif /* _INCLUDE__PLATFORM__IMX53__DRIVERS__TRUSTZONE_H_ */

22
base-hw/src/core/imx53/no_trustzone/pic.h Normal file
View File

@ -0,0 +1,22 @@
/*
* \brief Programmable interrupt controller for core
* \author Stefan Kalkowski
* \date 2012-10-24
*/
/*
* Copyright (C) 2012-2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _IMX53__PIC_H_
#define _IMX53__PIC_H_
/* core includes */
#include <pic_base.h>
namespace Kernel { class Pic : public Imx53::Pic_base { }; }
#endif /* _IMX53__PIC_H_ */

3
base-hw/src/core/imx53/platform_support.cc → base-hw/src/core/imx53/no_trustzone/platform_support.cc
View File

@ -69,7 +69,8 @@ Native_region * Platform::_ram_regions(unsigned const i)
{
static Native_region _regions[] =
{
{ Board::RAM_BASE, Board::RAM_SIZE }
{ Board::RAM0_BASE, Board::RAM0_SIZE },
{ Board::RAM1_BASE, Board::RAM1_SIZE }
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}

20
base-hw/src/core/imx53/no_trustzone/target.mk Normal file
View File

@ -0,0 +1,20 @@
#
# \brief Build config for Genodes core process
# \author Stefan Kalkowski
# \author Martin Stein
# \date 2012-10-24
#
# add include paths
INC_DIR += $(REP_DIR)/src/core/imx53/no_trustzone
ifeq ($(filter-out $(SPECS),trustzone),)
REQUIRES += no_trustzone
endif
# declare source paths
vpath platform_services.cc $(BASE_DIR)/src/core
vpath platform_support.cc $(REP_DIR)/src/core/imx53/no_trustzone
# include less specific target parts
include $(REP_DIR)/src/core/imx53/target.inc

3
base-hw/src/core/imx53/tlb.h → base-hw/src/core/imx53/no_trustzone/tlb.h
View File

@ -37,7 +37,8 @@ namespace Genode
*/
Core_tlb()
{
map_core_area(Board::RAM_BASE, Board::RAM_SIZE, 0);
map_core_area(Board::RAM0_BASE, Board::RAM0_SIZE, 0);
map_core_area(Board::RAM1_BASE, Board::RAM1_SIZE, 0);
map_core_area(Board::MMIO_BASE, Board::MMIO_SIZE, 1);
}
};

39
base-hw/src/core/imx53/pic.h → base-hw/src/core/imx53/pic_base.h
View File

@ -11,8 +11,8 @@
* under the terms of the GNU General Public License version 2.
*/
#ifndef _IMX53__PIC_H_
#define _IMX53__PIC_H_
#ifndef _IMX53__PIC_BASE_H_
#define _IMX53__PIC_BASE_H_
/* Genode includes */
#include <util/mmio.h>
@ -27,7 +27,7 @@ namespace Imx53
/**
* Programmable interrupt controller for core
*/
class Pic : public Mmio
class Pic_base : public Mmio
{
public:
@ -63,7 +63,7 @@ namespace Imx53
/**
* Interrupt security registers
*/
struct Intsec : Register_array<0x80, 32, MAX_INTERRUPT_ID+1, 1>
struct Intsec : Register_array<0x80, 32, MAX_INTERRUPT_ID, 1>
{
struct Nonsecure : Bitfield<0, 1> { };
};
@ -71,7 +71,7 @@ namespace Imx53
/**
* Interrupt set enable registers
*/
struct Enset : Register_array<0x100, 32, MAX_INTERRUPT_ID+1, 1, true>
struct Enset : Register_array<0x100, 32, MAX_INTERRUPT_ID, 1, true>
{
struct Set_enable : Bitfield<0, 1> { };
};
@ -79,7 +79,7 @@ namespace Imx53
/**
* Interrupt clear enable registers
*/
struct Enclear : Register_array<0x180, 32, MAX_INTERRUPT_ID+1, 1, true>
struct Enclear : Register_array<0x180, 32, MAX_INTERRUPT_ID, 1, true>
{
struct Clear_enable : Bitfield<0, 1> { };
};
@ -87,18 +87,15 @@ namespace Imx53
/**
* Interrupt priority level registers
*/
struct Icdipr : Register_array<0x400, 32, MAX_INTERRUPT_ID+1, 8>
struct Priority : Register_array<0x400, 32, MAX_INTERRUPT_ID, 8>
{
struct Priority : Bitfield<0, 8>
{
enum { GET_MIN_PRIORITY = 0xff };
};
enum { MIN_PRIO = 0xff };
};
/**
* Pending registers
*/
struct Pndr : Register_array<0xd00, 32, MAX_INTERRUPT_ID+1, 1>
struct Pndr : Register_array<0xd00, 32, MAX_INTERRUPT_ID, 1>
{
struct Pending : Bitfield<0, 1> { };
};
@ -106,7 +103,7 @@ namespace Imx53
/**
* Highest interrupt pending registers
*/
struct Hipndr : Register_array<0xd80, 32, MAX_INTERRUPT_ID+1, 1, true>
struct Hipndr : Register_array<0xd80, 32, MAX_INTERRUPT_ID, 1, true>
{
struct Pending : Bitfield<0, 1> { };
};
@ -121,18 +118,18 @@ namespace Imx53
/**
* Constructor, all interrupts get masked
*/
Pic() : Mmio(Board::TZIC_MMIO_BASE)
Pic_base() : Mmio(Board::TZIC_MMIO_BASE)
{
/* configure interrupts as nonsecure, and disable them */
for (unsigned i = 0; i <= MAX_INTERRUPT_ID; i++) {
write<Enclear::Clear_enable>(1, i);
write<Intsec::Nonsecure>(1, i);
write<Enclear::Clear_enable>(1, i);
}
write<Priomask::Mask>(0x1f);
write<Intctrl>(Intctrl::Enable::bits(1) |
Intctrl::Nsen::bits(1) |
Intctrl::Nsen_mask::bits(1));
Intctrl::Nsen::bits(1) |
Intctrl::Nsen_mask::bits(1));
}
/**
@ -141,7 +138,7 @@ namespace Imx53
bool take_request(unsigned & i)
{
for (unsigned j = 0; j <= MAX_INTERRUPT_ID; j++) {
if (read<Pndr::Pending>(j)) {
if (read<Hipndr::Pending>(j)) {
i = j;
return true;
}
@ -198,6 +195,4 @@ namespace Imx53
};
}
namespace Kernel { class Pic : public Imx53::Pic { }; }
#endif /* _IMX53__PIC_H_ */
#endif /* _IMX53__PIC_BASE_H_ */

11
base-hw/src/core/imx53/target.mk → base-hw/src/core/imx53/target.inc
View File

@ -6,7 +6,7 @@
#
# declare wich specs must be given to build this target
REQUIRES = platform_imx53
REQUIRES += platform_imx53
# add include paths
INC_DIR += $(REP_DIR)/src/core/imx53
@ -18,13 +18,11 @@ SRC_CC += platform_services.cc \
cpu_support.cc
# add assembly sources
SRC_S += mode_transition.s \
boot_modules.s \
crt0.s
SRC_S += mode_transition.s \
boot_modules.s \
crt0.s
# declare source paths
vpath platform_services.cc $(BASE_DIR)/src/core
vpath platform_support.cc $(REP_DIR)/src/core/imx53
vpath mode_transition.s $(REP_DIR)/src/core/arm_v7
vpath cpu_support.cc $(REP_DIR)/src/core/arm
vpath crt0.s $(REP_DIR)/src/core/arm
@ -42,4 +40,3 @@ endif
# include less specific target parts
include $(REP_DIR)/src/core/target.inc

222
base-hw/src/core/imx53/trustzone/csu.h Normal file
View File

@ -0,0 +1,222 @@
/*
* \brief Driver for the Central Security Unit
* \author Stefan Kalkowski
* \date 2012-11-06
*/
/*
* Copyright (C) 2012 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _SRC__SERVER__VMM__INCLUDE__CSU_H_
#define _SRC__SERVER__VMM__INCLUDE__CSU_H_
/* Genode includes */
#include <util/mmio.h>
#include <util/register.h>
namespace Genode
{
class Csu : Mmio
{
private:
template <off_t OFF>
struct Csl : public Register<OFF, 32>
{
enum {
SECURE = 0x33,
UNSECURE = 0xff,
};
struct Slave_a : Register<OFF, 32>::template Bitfield<0, 9> { };
struct Slave_b : Register<OFF, 32>::template Bitfield<16, 9> { };
};
struct Master : public Register<0x218, 32>
{
enum {
SECURE_UNLOCKED,
SECURE_LOCKED,
UNSECURE_UNLOCKED,
UNSECURE_LOCKED
};
struct Esdhc3 : Bitfield<0,2> { };
struct Cortex : Bitfield<2,2> { };
struct Sdma : Bitfield<4,2> { };
struct Gpu : Bitfield<6,2> { };
struct Usb : Bitfield<8,2> { };
struct Pata : Bitfield<10,2> { };
struct Mlb : Bitfield<14,2> { };
struct Rtic : Bitfield<18,2> { };
struct Esdhc4 : Bitfield<20,2> { };
struct Fec : Bitfield<22,2> { };
struct Dap : Bitfield<24,2> { };
struct Esdhc1 : Bitfield<26,2> { };
struct Esdhc2 : Bitfield<28,2> { };
};
struct Alarm_mask : public Register<0x230, 32> { };
struct Irq_ctrl : public Register<0x368, 32> { };
public:
typedef Csl<0x00> Csl00;
typedef Csl<0x04> Csl01;
typedef Csl<0x08> Csl02;
typedef Csl<0x0c> Csl03;
typedef Csl<0x10> Csl04;
typedef Csl<0x14> Csl05;
typedef Csl<0x18> Csl06;
typedef Csl<0x1c> Csl07;
typedef Csl<0x20> Csl08;
typedef Csl<0x24> Csl09;
typedef Csl<0x28> Csl10;
typedef Csl<0x2c> Csl11;
typedef Csl<0x30> Csl12;
typedef Csl<0x34> Csl13;
typedef Csl<0x38> Csl14;
typedef Csl<0x3c> Csl15;
typedef Csl<0x40> Csl16;
typedef Csl<0x44> Csl17;
typedef Csl<0x48> Csl18;
typedef Csl<0x4c> Csl19;
typedef Csl<0x50> Csl20;
typedef Csl<0x54> Csl21;
typedef Csl<0x58> Csl22;
typedef Csl<0x5c> Csl23;
typedef Csl<0x60> Csl24;
typedef Csl<0x64> Csl25;
typedef Csl<0x68> Csl26;
typedef Csl<0x6c> Csl27;
typedef Csl<0x70> Csl28;
typedef Csl<0x74> Csl29;
typedef Csl<0x78> Csl30;
typedef Csl<0x7c> Csl31;
Csu(addr_t const base) : Mmio(base)
{
/* Power (CCM, SRC, DPLLIP1-4, GPC and OWIRE) */
write<Csl09::Slave_a>(Csl00::UNSECURE);
/* AHBMAX S0-S2 */
write<Csl09::Slave_b>(Csl00::UNSECURE);
write<Csl20::Slave_a>(Csl00::UNSECURE);
write<Csl06::Slave_b>(Csl00::UNSECURE);
/* AHBMAX M6 */
write<Csl10::Slave_a>(Csl00::UNSECURE);
/* Timer (EPIT, GPT) TODO */
write<Csl04::Slave_a>(Csl00::UNSECURE);
/* UART 1-5 */
write<Csl07::Slave_b>(Csl00::UNSECURE);
write<Csl08::Slave_a>(Csl00::UNSECURE);
write<Csl26::Slave_a>(Csl00::UNSECURE);
write<Csl30::Slave_b>(Csl00::UNSECURE);
write<Csl19::Slave_a>(Csl00::UNSECURE);
/* GPIO */
//write<Csl00::Slave_b>(Csl00::UNSECURE);
//write<Csl01::Slave_a>(Csl00::UNSECURE);
//write<Csl01::Slave_b>(Csl00::UNSECURE);
//write<Csl02::Slave_a>(Csl00::UNSECURE);
/* IOMUXC TODO */
write<Csl05::Slave_a>(Csl00::UNSECURE);
/* SDMA TODO */
write<Csl15::Slave_a>(Csl00::UNSECURE);
/* USB */
write<Csl00::Slave_a>(Csl00::UNSECURE);
/* TVE */
//write<Csl22::Slave_b>(Csl00::UNSECURE);
/* I2C */
//write<Csl18::Slave_a>(Csl00::UNSECURE);
//write<Csl17::Slave_b>(Csl00::UNSECURE);
//write<Csl31::Slave_a>(Csl00::UNSECURE);
/* IPU */
//write<Csl24::Slave_a>(Csl00::UNSECURE);
/* Audio */
write<Csl18::Slave_b>(Csl00::UNSECURE);
/* SATA */
write<Csl07::Slave_a>(Csl00::UNSECURE);
/* FEC */
write<Csl22::Slave_a>(Csl00::UNSECURE);
/* SDHCI 1-4 */
write<Csl25::Slave_a>(Csl00::UNSECURE);
write<Csl25::Slave_b>(Csl00::UNSECURE);
write<Csl28::Slave_a>(Csl00::UNSECURE);
write<Csl28::Slave_b>(Csl00::UNSECURE);
/* SPDIF */
write<Csl29::Slave_a>(Csl00::UNSECURE);
/* GPU 2D */
write<Csl24::Slave_b>(Csl00::UNSECURE);
/* GPU 3D */
write<Csl27::Slave_b>(Csl00::UNSECURE);
write<Csl02::Slave_b>(Csl00::UNSECURE);
write<Csl03::Slave_a>(Csl00::UNSECURE);
write<Csl03::Slave_b>(Csl00::UNSECURE);
write<Csl04::Slave_b>(Csl00::UNSECURE); // SRTC
write<Csl05::Slave_b>(Csl00::UNSECURE);
write<Csl06::Slave_a>(Csl00::UNSECURE);
write<Csl08::Slave_b>(Csl00::UNSECURE);
write<Csl10::Slave_b>(Csl00::UNSECURE);
write<Csl11::Slave_a>(Csl00::UNSECURE);
write<Csl11::Slave_b>(Csl00::UNSECURE);
write<Csl12::Slave_a>(Csl00::UNSECURE);
write<Csl12::Slave_b>(Csl00::UNSECURE);
write<Csl13::Slave_a>(Csl00::UNSECURE);
write<Csl13::Slave_b>(Csl00::UNSECURE);
write<Csl14::Slave_a>(Csl00::UNSECURE);
write<Csl14::Slave_b>(Csl00::UNSECURE);
write<Csl15::Slave_b>(Csl00::UNSECURE); // SCC
write<Csl16::Slave_a>(Csl00::UNSECURE);
write<Csl16::Slave_b>(Csl00::UNSECURE); // RTIC
write<Csl17::Slave_a>(Csl00::UNSECURE);
write<Csl19::Slave_b>(Csl00::UNSECURE);
write<Csl20::Slave_b>(Csl00::UNSECURE);
write<Csl21::Slave_a>(Csl00::UNSECURE);
write<Csl21::Slave_b>(Csl00::UNSECURE);
//write<Csl23::Slave_a>(Csl00::UNSECURE); //VPU
write<Csl23::Slave_b>(Csl00::UNSECURE);
write<Csl26::Slave_b>(Csl00::UNSECURE);
write<Csl27::Slave_a>(Csl00::UNSECURE);
write<Csl29::Slave_b>(Csl00::UNSECURE);
write<Csl30::Slave_a>(Csl00::UNSECURE);
write<Csl31::Slave_b>(Csl00::UNSECURE);
write<Master::Sdma>(Master::UNSECURE_UNLOCKED);
write<Master::Esdhc3>(Master::UNSECURE_UNLOCKED);
write<Master::Gpu>(Master::UNSECURE_UNLOCKED);
write<Master::Usb>(Master::UNSECURE_UNLOCKED);
write<Master::Pata>(Master::UNSECURE_UNLOCKED);
write<Master::Esdhc4>(Master::UNSECURE_UNLOCKED);
write<Master::Fec>(Master::UNSECURE_UNLOCKED);
write<Master::Dap>(Master::UNSECURE_UNLOCKED);
write<Master::Esdhc1>(Master::UNSECURE_UNLOCKED);
write<Master::Esdhc2>(Master::UNSECURE_UNLOCKED);
}
};
}
#endif /* _BASE_HW__SRC__SERVER__VMM__TSC_380_H_ */

64
base-hw/src/core/imx53/trustzone/pic.h Normal file
View File

@ -0,0 +1,64 @@
/*
* \brief Programmable interrupt controller for core
* \author Stefan Kalkowski
* \date 2012-10-24
*/
/*
* Copyright (C) 2012-2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _IMX53__PIC_H_
#define _IMX53__PIC_H_
/* Genode includes */
#include <util/mmio.h>
/* core includes */
#include <pic_base.h>
namespace Imx53
{
using namespace Genode;
/**
* Programmable interrupt controller for core
*/
class Pic : public Pic_base
{
public:
Pic()
{
for (unsigned i = 0; i <= MAX_INTERRUPT_ID; i++) {
write<Intsec::Nonsecure>(0, i);
write<Priority>(0, i);
}
write<Priomask::Mask>(0xff);
}
void unsecure(unsigned const i)
{
if (i <= MAX_INTERRUPT_ID) {
write<Intsec::Nonsecure>(1, i);
write<Priority>(0x80, i);
}
}
void secure(unsigned const i)
{
if (i <= MAX_INTERRUPT_ID) {
write<Intsec::Nonsecure>(0, i);
write<Priority>(0, i);
}
}
};
}
namespace Kernel { class Pic : public Imx53::Pic { }; }
#endif /* _IMX53__PIC_H_ */

44
base-hw/src/core/imx53/trustzone/platform_services.cc Normal file
View File

@ -0,0 +1,44 @@
/*
* \brief Platform specific services for base-hw (TrustZone)
* \author Stefan Kalkowski
* \date 2012-10-26
*/
/*
* Copyright (C) 2012-2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
/* Genode includes */
#include <base/service.h>
#include <drivers/trustzone.h>
/* Core includes */
#include <platform.h>
#include <platform_services.h>
#include <vm_root.h>
/*
* Add TrustZone specific vm service
*/
void Genode::platform_add_local_services(Genode::Rpc_entrypoint *ep,
Genode::Sliced_heap *sh,
Genode::Service_registry *ls)
{
using namespace Genode;
/*
* We use an extra portion of RAM for the VM state,
* so we can map it non-cached to core instead of normal, cached RAM.
* In future, when core only maps memory on demand, this extra allocator,
* can be eliminated.
*/
static Synchronized_range_allocator<Allocator_avl> vm_alloc(0);
vm_alloc.add_range(Trustzone::VM_STATE_BASE, Trustzone::VM_STATE_SIZE);
static Vm_root vm_root(ep, sh, &vm_alloc);
static Local_service vm_ls(Vm_session::service_name(), &vm_root);
ls->insert(&vm_ls);
}

113
base-hw/src/core/imx53/trustzone/platform_support.cc Normal file
View File

@ -0,0 +1,113 @@
/*
* \brief Specific core implementations
* \author Stefan Kalkowski
* \date 2012-10-24
*/
/*
* Copyright (C) 2012-2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#include <drivers/trustzone.h>
/* core includes */
#include <platform.h>
#include <board.h>
#include <pic.h>
#include <cpu.h>
#include <kernel/irq.h>
using namespace Genode;
namespace Kernel { void init_platform(); }
/**
* Interrupts that core shall provide to users
*/
static unsigned irq_ids[] =
{
Board::EPIT_2_IRQ,
Board::GPIO1_IRQL,
Board::GPIO1_IRQH,
Board::GPIO2_IRQL,
Board::GPIO2_IRQH,
Board::GPIO3_IRQL,
Board::GPIO3_IRQH,
Board::GPIO4_IRQL,
Board::GPIO4_IRQH,
Board::GPIO5_IRQL,
Board::GPIO5_IRQH,
Board::GPIO6_IRQL,
Board::GPIO6_IRQH,
Board::GPIO7_IRQL,
Board::GPIO7_IRQH,
Board::I2C_2_IRQ,
Board::I2C_3_IRQ
};
enum { IRQ_IDS_SIZE = sizeof(irq_ids)/sizeof(irq_ids[0]) };
void Kernel::init_platform()
{
/* make user IRQs become known by cores IRQ session backend and kernel */
static uint8_t _irqs[IRQ_IDS_SIZE][sizeof(Irq)];
for (unsigned i = 0; i < IRQ_IDS_SIZE; i++) {
new (_irqs[i]) Irq(irq_ids[i]);
}
}
unsigned * Platform::_irq(unsigned const i)
{
return i < IRQ_IDS_SIZE ? &irq_ids[i] : 0;
}
Native_region * Platform::_ram_regions(unsigned const i)
{
static Native_region _regions[] =
{
{ Trustzone::SECURE_RAM_BASE, Trustzone::SECURE_RAM_SIZE },
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}
Native_region * Platform::_mmio_regions(unsigned const i)
{
static Native_region _regions[] =
{
{ 0x07000000, 0x1000000 }, /* security controller */
{ 0x10000000, 0x30000000 }, /* SATA, IPU, GPU */
{ 0x50000000, 0x20000000 }, /* Misc. */
{ Trustzone::NONSECURE_RAM_BASE, Trustzone::NONSECURE_RAM_SIZE },
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}
Native_region * Platform::_core_only_mmio_regions(unsigned const i)
{
static Native_region _regions[] =
{
/* core UART */
{ Board::UART_1_MMIO_BASE, Board::UART_1_MMIO_SIZE },
/* core timer */
{ Board::EPIT_1_MMIO_BASE, Board::EPIT_1_MMIO_SIZE },
/* interrupt controller */
{ Board::TZIC_MMIO_BASE, Board::TZIC_MMIO_SIZE },
/* vm state memory */
{ Trustzone::VM_STATE_BASE, Trustzone::VM_STATE_SIZE },
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}
Cpu::User_context::User_context() { cpsr = Psr::init_user_with_trustzone(); }

27
base-hw/src/core/imx53/trustzone/target.mk Normal file
View File

@ -0,0 +1,27 @@
#
# \brief Build config for Genodes core process
# \author Stefan Kalkowski
# \author Martin Stein
# \date 2012-10-24
#
REQUIRES += trustzone
# add include paths
INC_DIR += $(REP_DIR)/src/core/imx53/trustzone
# adjust link address of a trustzone text segment
LD_TEXT_ADDR = 0x70800000
# add C++ sources
SRC_CC += vm_session_component.cc
# declare source paths
vpath platform_services.cc $(BASE_DIR)/src/core/imx53/trustzone
vpath platform_support.cc $(REP_DIR)/src/core/imx53/trustzone
vpath trustzone.cc $(REP_DIR)/src/core/imx53/trustzone
vpath vm_session_component.cc $(REP_DIR)/src/core
# include less specific target parts
include $(REP_DIR)/src/core/imx53/target.inc

52
base-hw/src/core/imx53/trustzone/tlb.h Normal file
View File

@ -0,0 +1,52 @@
/*
* \brief Translation lookaside buffer
* \author Stefan Kalkowski
* \author Martin Stein
* \date 2012-10-24
*/
/*
* Copyright (C) 2012-2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _IMX53__TLB_H_
#define _IMX53__TLB_H_
#include <drivers/trustzone.h>
/* core includes */
#include <board.h>
#include <tlb/arm_v7.h>
namespace Genode
{
struct Page_flags : Arm::Page_flags { };
class Tlb : public Arm_v7::Section_table { };
/**
* Translation lookaside buffer of core
*/
class Core_tlb : public Tlb
{
public:
/**
* Constructor - ensures that core never gets a pagefault
*/
Core_tlb()
{
map_core_area(Trustzone::SECURE_RAM_BASE,
Trustzone::SECURE_RAM_SIZE, 0);
map_core_area(Board::MMIO_BASE, Board::MMIO_SIZE, 1);
map_core_area(Trustzone::VM_STATE_BASE,
Trustzone::VM_STATE_SIZE, 1);
}
};
}
#endif /* _IMX53__TLB_H_ */

46
base-hw/src/core/imx53/trustzone/trustzone.cc Normal file
View File

@ -0,0 +1,46 @@
/*
* \brief TrustZone specific functions for Versatile Express
* \author Stefan Kalkowski
* \date 2012-10-10
*/
/*
* Copyright (C) 2012-2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
/* core includes */
#include <trustzone.h>
#include <pic.h>
#include <cpu.h>
#include <csu.h>
#include <board.h>
/* monitor exception vector address */
extern int _mon_kernel_entry;
void Kernel::trustzone_initialization(Pic *pic)
{
/* set exception vector entry */
Genode::Cpu::mon_exception_entry_at((Genode::addr_t)&_mon_kernel_entry);
/* enable coprocessor access for TZ VMs */
Genode::Cpu::allow_coprocessor_nonsecure();
/* configure non-secure interrupts */
for (unsigned i = 0; i <= Pic::MAX_INTERRUPT_ID; i++) {
if ((i != Imx53::Board::EPIT_1_IRQ) &&
(i != Imx53::Board::EPIT_2_IRQ) &&
(i != Imx53::Board::I2C_2_IRQ) &&
(i != Imx53::Board::I2C_3_IRQ) &&
(i < Imx53::Board::GPIO1_IRQL || i > Imx53::Board::GPIO4_IRQH) &&
(i < Imx53::Board::GPIO5_IRQL || i > Imx53::Board::GPIO7_IRQH))
pic->unsecure(i);
}
/* configure central security unit */
Genode::Csu csu(0x63f9c000);
}

17
base-hw/src/core/kernel/vm.h
View File

@ -22,6 +22,7 @@
#include <kernel/kernel.h>
#include <kernel/pd.h>
#include <kernel/signal_receiver.h>
#include <cpu.h>
namespace Kernel
{
@ -42,8 +43,13 @@ class Kernel::Vm : public Object<Vm, MAX_VMS, Vm_ids, vm_ids, vm_pool>,
{
private:
Genode::Cpu_state_modes * const _state;
Signal_context * const _context;
struct Vm_state : Genode::Cpu_state_modes
{
Genode::addr_t dfar;
};
Vm_state * const _state;
Signal_context * const _context;
public:
@ -53,10 +59,11 @@ class Kernel::Vm : public Object<Vm, MAX_VMS, Vm_ids, vm_ids, vm_pool>,
* \param state initial CPU state
* \param context signal for VM exceptions other than interrupts
*/
Vm(Genode::Cpu_state_modes * const state,
Vm(void * const state,
Signal_context * const context)
:
Execution_context(Priority::MIN), _state(state), _context(context)
Execution_context(Priority::MIN),
_state((Vm_state * const)state), _context(context)
{ }
@ -80,6 +87,8 @@ class Kernel::Vm : public Object<Vm, MAX_VMS, Vm_ids, vm_ids, vm_pool>,
case Genode::Cpu_state::FAST_INTERRUPT_REQUEST:
handle_interrupt();
return;
case Genode::Cpu_state::DATA_ABORT:
_state->dfar = Genode::Cpu::Dfar::read();
default:
cpu_scheduler()->remove(this);
_context->submit(1);

6
base/include/platform/imx53/drivers/board_base.h
View File

@ -25,8 +25,10 @@ namespace Genode
MMIO_BASE = 0x0,
MMIO_SIZE = 0x70000000,
RAM_BASE = 0x70000000,
RAM_SIZE = 0x40000000,
RAM0_BASE = 0x70000000,
RAM0_SIZE = 0x20000000,
RAM1_BASE = 0xb0000000,
RAM1_SIZE = 0x20000000,
UART_1_IRQ = 31,
UART_1_MMIO_BASE = 0x53fbc000,