mirror of
https://github.com/genodelabs/genode.git
synced 2025-04-08 11:55:24 +00:00
parent
24b1f269be
commit
49b3d520a9
@ -74,6 +74,20 @@ struct Genode::Exynos5
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/* SD card */
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SDMMC0_IRQ = 107,
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/******************************
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** HDMI memory map and irqs **
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******************************/
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/* Mixer base */
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MIXER_BASE = 0x14450000,
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/* HDMI base */
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HDMI_BASE = 0x14530000,
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/* I2C BASE */
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I2C_BASE = 0x12ce0000,
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/* I2C */
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I2C_HDMI_IRQ = 96,
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};
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@ -35,11 +35,46 @@ struct Genode::Board_base : Exynos4
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/* power management unit */
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PMU_MMIO_BASE = 0x10020000,
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PMU_MMIO_SIZE = 0x5000, /* TODO Check the region size */
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PMU_MMIO_SIZE = 0x5000,
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/* UART */
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UART_1_MMIO_BASE = 0x13810000,
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UART_1_IRQ = 85,
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UART_1_CLOCK = 100000000, /* TODO Check SCLK_UART1 */
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/* USB HOST interrupt */
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UART_2_MMIO_BASE = 0x13820000,
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UART_2_IRQ = 86,
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UART_2_CLOCK = 100000000, /* TODO Check SCLK_UART2 */
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MCT_IRQ_L0 = 28,
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MCT_IRQ_L1 = 28,
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MCT_IRQ_L2 = 28,
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MCT_IRQ_L3 = 28,
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TIMER_IRQ = 28,
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/* USB IRQ */
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USB_HOST20_IRQ = 102,
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/******************************
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** HDMI memory map and irqs **
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******************************/
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/* Mixer base */
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MIXER_BASE = 0x12C10000,
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/* HDMI base */
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HDMI_BASE = 0x12D00000,
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/* IC2 BASE*/
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I2C_BASE = 0x138E0000,
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/* HDMI IRQ*/
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I2C_HDMI_IRQ = 125,
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/* wether board provides security extension */
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SECURITY_EXTENSION = 0, /* TODO Check this value */
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};
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};
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@ -7,7 +7,7 @@
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#
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# denote specs that are fullfilled by this spec
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SPECS += exynos exynos4 cortex_a9 usb
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SPECS += exynos exynos4 cortex_a9 usb framebuffer
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# add repository relative paths
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REP_INC_DIR += include/spec/odroid_x2
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@ -417,7 +417,7 @@ class Video_mixer : public Attached_mmio
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/**
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* Constructor
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*/
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Video_mixer() : Attached_mmio(0x14450000, 0x10000) { }
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Video_mixer() : Attached_mmio(Genode::Board_base::MIXER_BASE, 0x10000) { }
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/**
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* Initialize mixer for displaying one graphical input fullscreen
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@ -520,14 +520,16 @@ class Video_mixer : public Attached_mmio
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cfg = read<Cfg>();
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switch (fb_height) {
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case 480:
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Cfg::Hd_sd::set(cfg, 0);
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Cfg::Hd_sd::set(cfg, 1);
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Cfg::Hd_mode::set(cfg, 1);
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break;
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case 576:
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Cfg::Hd_sd::set(cfg, 0);
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Cfg::Hd_sd::set(cfg, 1);
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Cfg::Hd_mode::set(cfg, 1);
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break;
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case 720:
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Cfg::Hd_sd::set(cfg, 1);
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Cfg::Hd_mode::set(cfg, 0);
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Cfg::Hd_mode::set(cfg, 1);
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break;
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case 1080:
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Cfg::Hd_sd::set(cfg, 1);
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@ -577,7 +579,7 @@ class I2c_hdmi : public I2c_interface
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* Constructor
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*/
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I2c_hdmi()
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: I2c_interface(0x12ce0000, Genode::Board_base::I2C_HDMI_IRQ) { }
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: I2c_interface(Genode::Board_base::I2C_BASE, Genode::Board_base::I2C_HDMI_IRQ) { }
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/**
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* Stop HDMI PHY from operating
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@ -960,7 +962,7 @@ class Hdmi : public Attached_mmio
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* Constructor
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*/
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Hdmi()
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: Attached_mmio(0x14530000, 0xa0000), _i2c_hdmi() { }
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: Attached_mmio(Genode::Board_base::HDMI_BASE, 0xa0000), _i2c_hdmi() { }
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/**
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* Initialize HDMI controller for video output only
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@ -1,5 +1,5 @@
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TARGET = fb_drv
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REQUIRES = exynos5
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REQUIRES = exynos
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SRC_CC += main.cc driver.cc
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LIBS += base config server
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INC_DIR += $(PRG_DIR)
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@ -136,23 +136,14 @@ class Cmu : public Regulator::Driver,
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typedef Pll_lock<0x0008> Mpll_lock;
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typedef Pll_con0<0x0108> Mpll_con0;
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struct Clk_src_dmc : Register<0x10200, 32>
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{
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struct Mux_mpll_sel : Bitfield<12, 1> { enum { XXTI, MPLL_FOUT_RGT }; };
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};
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struct Clk_gate_ip_acp : Register<0x0900, 32> { };
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struct Clk_gate_ip_isp0 : Register<0x8800, 32> { };
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struct Clk_gate_ip_isp1 : Register<0x8804, 32> { };
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/***********************
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** CMU TOP registers **
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***********************/
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struct Clk_gate_ip_tv : Register<0x10928, 32>
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{
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struct Clk_mixer : Bitfield<1, 1> { };
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struct Clk_hdmi : Bitfield<3, 1> { };
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};
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struct Clk_gate_ip_fsys : Register<0xC940, 32>
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{
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@ -161,7 +152,27 @@ class Cmu : public Regulator::Driver,
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};
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struct Clk_src_tv : Register<0xC224, 32> /* old name Clk_src_disp1_0 */
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{
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struct Hdmi_sel : Bitfield<0, 1> { };
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};
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struct Clk_src_mask_tv : Register<0xC324, 32>
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{
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struct Hdmi_mask : Bitfield<0, 1> { };
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};
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struct Clk_gate_ip_peric : Register<0xC950, 32>
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{
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struct Clk_uart2 : Bitfield<2, 1> { };
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struct Clk_i2chdmi : Bitfield<14, 1> { };
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struct Clk_pwm : Bitfield<24, 1> { };
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};
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struct Clk_gate_block : Register<0xC970, 32>
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{
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struct Clk_tv : Bitfield<1, 1> { };
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};
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/*******************
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** CPU functions **
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@ -245,6 +256,25 @@ class Cmu : public Regulator::Driver,
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}
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/**********************
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** Device functions **
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**********************/
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void _hdmi_enable()
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{
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write<Clk_gate_ip_peric::Clk_i2chdmi>(1);
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Clk_gate_ip_tv::access_t gd1 = read<Clk_gate_ip_tv>();
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Clk_gate_ip_tv::Clk_mixer::set(gd1, 1);
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Clk_gate_ip_tv::Clk_hdmi::set(gd1, 1);
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write<Clk_gate_ip_tv>(gd1);
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write<Clk_gate_block::Clk_tv>(1);
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write<Clk_src_mask_tv::Hdmi_mask>(1);
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write<Clk_src_tv::Hdmi_sel>(1);
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}
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void _enable(Regulator_id id)
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{
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switch (id) {
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@ -253,6 +283,10 @@ class Cmu : public Regulator::Driver,
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write<Clk_gate_ip_fsys::Usbdevice>(1);
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return write<Clk_gate_ip_fsys::Usbhost20>(1);
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}
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case CLK_HDMI:
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_hdmi_enable();
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break;
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default:
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PWRN("Unsupported for %s", names[id].name);
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}
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@ -281,23 +315,19 @@ class Cmu : public Regulator::Driver,
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Genode::Board_base::CMU_MMIO_SIZE),
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_cpu_freq(CPU_FREQ_1400)
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{
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/**
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* Close certain clock gates by default (~ 0.7 Watt reduction)
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*/
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write<Clk_gate_ip_fsys>(0);
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write<Clk_gate_ip_peric::Clk_uart2>(1);
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write<Clk_gate_ip_peric::Clk_pwm>(1);
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/**
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* Set default CPU frequency
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*/
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_cpu_clk_freq(_cpu_freq);
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}
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/********************************
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** Regulator driver interface **
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********************************/
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@ -334,7 +364,6 @@ class Cmu : public Regulator::Driver,
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bool state(Regulator_id id)
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{
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switch (id) {
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case CLK_USB20:
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return read<Clk_gate_ip_fsys::Usbhost20>();
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@ -32,9 +32,14 @@ struct Driver_factory: Regulator::Driver_factory
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switch (id) {
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case Regulator::CLK_CPU:
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case Regulator::CLK_USB20:
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case Regulator::CLK_HDMI:
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return _cmu;
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case Regulator::PWR_USB20:
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case Regulator::PWR_HDMI:
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return _pmu;
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default:
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throw Root::Invalid_args(); /* invalid regulator */
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};
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@ -69,7 +69,6 @@ class Pmu : public Regulator::Driver,
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typedef Control<0x0708> Usbhost_phy1_control;
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typedef Control<0x70c> Usbhost_phy2_control;
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void _enable(unsigned long id)
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{
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switch (id) {
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@ -78,6 +77,13 @@ class Pmu : public Regulator::Driver,
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write<Usbhost_phy1_control::Enable>(1);
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write<Usbhost_phy2_control::Enable>(1);
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break;
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case PWR_HDMI: {
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Hdmi_phy_control::access_t hpc = read<Hdmi_phy_control>();
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Hdmi_phy_control::Div_ratio::set(hpc, 150);
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Hdmi_phy_control::Enable::set(hpc, 1);
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write<Hdmi_phy_control>(hpc);
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break; }
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default:
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PWRN("Unsupported for %s", names[id].name);
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}
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@ -91,6 +97,9 @@ class Pmu : public Regulator::Driver,
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write<Usbhost_phy1_control::Enable>(0);
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write<Usbhost_phy2_control::Enable>(0);
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break;
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case PWR_HDMI:
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write<Hdmi_phy_control::Enable>(0);
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break;
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default:
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PWRN("Unsupported for %s", names[id].name);
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}
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@ -104,9 +113,10 @@ class Pmu : public Regulator::Driver,
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Pmu() : Genode::Attached_mmio(Genode::Board_base::PMU_MMIO_BASE,
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Genode::Board_base::PMU_MMIO_SIZE)
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{
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write<Usbdrd_phy_control ::Enable>(0);
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write<Usbdrd_phy_control::Enable>(0);
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write<Usbhost_phy1_control::Enable>(0);
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write<Usbhost_phy2_control::Enable>(0);
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write<Hdmi_phy_control::Enable>(0);
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}
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