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Defs for the boards, supported by 'base-hw'
This commit is contained in:
Martin Stein
Christian Helmuth
parent
4b90cba132
commit
2eccfc5dc9
53
base/include/drivers/board/panda_a2.h
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53
base/include/drivers/board/panda_a2.h
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/**
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* \brief Driver for the OMAP4 PandaBoard revision A2
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* \author Martin stein
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* \date 2011-11-03
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*/
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/*
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* Copyright (C) 2011-2012 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _BASE__INCLUDE__DRIVERS__BOARD__PANDA_A2_H_
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#define _BASE__INCLUDE__DRIVERS__BOARD__PANDA_A2_H_
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namespace Genode
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{
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/**
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* Driver for the OMAP4 PandaBoard revision A2
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*/
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struct Panda_a2
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{
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enum
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{
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/* Buses */
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L4_PER_BASE = 0x48000000,
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L4_PER_SIZE = 0x01000000,
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/* Clocks */
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MPU_DPLL_CLOCK = 200*1000*1000,
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/* UART */
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TL16C750_3_MMIO_BASE = L4_PER_BASE + 0x20000,
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TL16C750_3_MMIO_SIZE = 0x2000,
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TL16C750_3_CLOCK = 48*1000*1000,
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TL16C750_3_IRQ = 74,
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/* CPU */
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CORTEX_A9_PRIVATE_MEM_BASE = L4_PER_BASE + 0x240000,
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CORTEX_A9_PRIVATE_MEM_SIZE = 0x2000,
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CORTEX_A9_CLOCK = MPU_DPLL_CLOCK,
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CORTEX_A9_SECURITY_EXTENSION = 0,
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/* RAM */
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EMIF1_EMIF2_CS0_SDRAM_BASE = 0x80000000,
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EMIF1_EMIF2_CS0_SDRAM_SIZE = 0x40000000,
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};
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};
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}
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#endif /* _BASE__INCLUDE__DRIVERS__BOARD__PANDA_A2_H_ */
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78
base/include/drivers/board/pbxa9.h
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78
base/include/drivers/board/pbxa9.h
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/**
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* \brief Driver for the Realview PBXA9 board
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* \author Martin stein
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* \date 2011-11-03
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*/
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/*
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* Copyright (C) 2011-2012 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _BASE__INCLUDE__DRIVERS__BOARD__PBXA9_H_
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#define _BASE__INCLUDE__DRIVERS__BOARD__PBXA9_H_
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namespace Genode
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{
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/**
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* Driver for the Realview PBXA9 board
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*/
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struct Pbxa9
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{
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enum
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{
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/* Northbridge */
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NORTHBRIDGE_DDR_0_BASE = 0x00000000, /* DMC mirror */
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NORTHBRIDGE_DDR_0_SIZE = 256*1024*1024,
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NORTHBRIDGE_AHB_BASE = 0x10020000,
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NORTHBRIDGE_AHB_SIZE = 768*1024,
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/* Southbridge */
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SOUTHBRIDGE_APB_BASE = 0x10000000,
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SOUTHBRIDGE_APB_SIZE = 128*1024,
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/* Clocks */
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OSC_6_CLOCK = 24*1000*1000,
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OSC_7_CLOCK = 14*1000*1000,
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/* CPU */
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CORTEX_A9_CLOCK = OSC_7_CLOCK * 5,
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CORTEX_A9_PRIVATE_MEM_BASE = 0x1f000000,
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CORTEX_A9_PRIVATE_MEM_SIZE = 0x01000000,
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CORTEX_A9_SECURITY_EXTENSION = 0,
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/* UART */
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PL011_0_MMIO_BASE = SOUTHBRIDGE_APB_BASE + 0x9000,
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PL011_0_MMIO_SIZE = 4*1024,
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PL011_0_CLOCK = OSC_6_CLOCK,
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PL011_0_IRQ = 44,
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/* Timer */
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SP804_0_MMIO_BASE = SOUTHBRIDGE_APB_BASE + 0x11000,
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SP804_0_MMIO_SIZE = 4*1024,
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SP804_0_IRQ = 36,
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SP804_0_CLOCK = 1*1000*1000,
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SP804_1_MMIO_BASE = SOUTHBRIDGE_APB_BASE + 0x12000,
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SP804_1_MMIO_SIZE = 4*1024,
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SP804_1_IRQ = 37,
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SP804_1_CLOCK = 1*1000*1000,
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SP804_2_MMIO_BASE = SOUTHBRIDGE_APB_BASE + 0x18000,
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SP804_2_MMIO_SIZE = 4*1024,
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SP804_2_IRQ = 73,
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SP804_2_CLOCK = 1*1000*1000,
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SP804_3_MMIO_BASE = SOUTHBRIDGE_APB_BASE + 0x19000,
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SP804_3_MMIO_SIZE = 4*1024,
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SP804_3_IRQ = 74,
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SP804_3_CLOCK = 1*1000*1000,
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};
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};
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}
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#endif /* _BASE__INCLUDE__DRIVERS__BOARD__PBXA9_H_ */
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64
base/include/drivers/board/vea9x4.h
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64
base/include/drivers/board/vea9x4.h
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/**
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* \brief Driver for the Versatile Express A9X4 board
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* \author Martin stein
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* \date 2011-11-03
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*/
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/*
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* Copyright (C) 2011-2012 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _BASE__INCLUDE__DRIVERS__BOARD__VEA9X4_H_
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#define _BASE__INCLUDE__DRIVERS__BOARD__VEA9X4_H_
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namespace Genode
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{
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/**
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* Driver for the Versatile Express A9X4 board
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*
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* \detail Implies the uATX motherboard and the
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* CoreTile Express A9X4 daughterboard
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*/
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struct Vea9x4
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{
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enum
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{
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/* Static memory bus */
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SMB_CS7_BASE = 0x10000000,
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SMB_CS7_SIZE = 0x20000,
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SMB_CS0_TO_CS6_BASE = 0x40000000,
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SMB_CS0_TO_CS6_SIZE = 0x20000000,
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/* UART */
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PL011_0_MMIO_BASE = SMB_CS7_BASE + 0x9000,
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PL011_0_MMIO_SIZE = 0x1000,
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PL011_0_CLOCK = 24*1000*1000,
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PL011_0_IRQ = 5,
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/* Timer/counter */
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SP804_0_1_MMIO_BASE = SMB_CS7_BASE + 0x11000,
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SP804_0_1_MMIO_SIZE = 0x1000,
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SP804_0_1_CLOCK = 1000*1000,
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SP804_0_1_IRQ = 34,
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/* Clocks */
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TCREF_CLOCK = 66670*1000,
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/* CPU */
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CORTEX_A9_PRIVATE_MEM_BASE = 0x1e000000,
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CORTEX_A9_PRIVATE_MEM_SIZE = 0x2000,
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CORTEX_A9_CLOCK = TCREF_CLOCK,
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CORTEX_A9_SECURITY_EXTENSION = 1,
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/* RAM */
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LOCAL_DDR2_BASE = 0x60000000,
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LOCAL_DDR2_SIZE = 0x40000000,
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};
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};
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}
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#endif /* _BASE__INCLUDE__DRIVERS__BOARD__VEA9X4_H_ */
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