base-hw: flush cached zeroes in 'clear_ds(...)'

Ref #706

base-hw/include/kernel/syscalls.h

@@ -60,6 +60,7 @@ namespace Kernel
 		/* management of resource protection-domains */
 		SET_PAGER = 11,
 		UPDATE_PD = 12,
+		UPDATE_REGION = 32,
 		NEW_PD = 13,
 
 		/* interrupt handling */
@@ -169,13 +170,27 @@ namespace Kernel
 	 * applied from the moment it returns to the userland. This syscall is
 	 * inappropriate in case that a PD wants to change its own configuration.
 	 * There's no need for this syscall after a configuration change that
-	 * can't affect the kernel and/or hardware caches.
+	 * can't affect the kernel- and/or hardware-caches.
 	 *
 	 * Restricted to core threads.
 	 */
 	inline void update_pd(unsigned const pd_id) {
 		syscall(UPDATE_PD, (Syscall_arg)pd_id); }
 
+	/**
+	 * Propagate memory-updates within a given virtual region
+	 *
+	 * \param base  virtual base of the region
+	 * \param size  size of the region
+	 *
+	 * If one updates a memory region and must ensure that the update
+	 * gets visible directly to other address spaces, this syscall does
+	 * the job.
+	 *
+	 * Restricted to core threads.
+	 */
+	inline void update_region(addr_t base, size_t size) {
+		syscall(UPDATE_REGION, (Syscall_arg)base, (Syscall_arg)size); }
 
 	/**
 	 * Create a new thread that is stopped initially

base-hw/src/core/cpu/arm.h

@@ -18,6 +18,10 @@
 #include <util/register.h>
 #include <cpu/cpu_state.h>
 
+/* local includes */
+#include <board.h>
+#include <util.h>
+
 namespace Arm
 {
 	using namespace Genode;
@@ -637,6 +641,22 @@ namespace Arm
 			asm volatile ("mcr p15, 0, %[rd], c8, c7, 0" :: [rd]"r"(0) : );
 			flush_caches();
 		}
+
+		/*
+		 * Clean every data-cache entry within a region via MVA
+		 */
+		static void flush_data_cache_by_virt_region(addr_t base, size_t const size)
+		{
+			enum {
+				CACHE_LINE_SIZE        = 1 << Board::CACHE_LINE_SIZE_LOG2,
+				CACHE_LINE_ALIGNM_MASK = ~(CACHE_LINE_SIZE - 1),
+			};
+			addr_t const top = base + size;
+			base = base & CACHE_LINE_ALIGNM_MASK;
+			for (; base < top; base += CACHE_LINE_SIZE)
+				asm volatile ("mcr p15, 0, %[base], c7, c10, 1\n" /* DCCMVAC */
+				              :: [base] "r" (base) : );
+		}
 	};
 }
 

base-hw/src/core/kernel.cc

@@ -1092,6 +1092,19 @@ namespace Kernel
 	}
 
 
+	/**
+	 * Do specific syscall for 'user', for details see 'syscall.h'
+	 */
+	void do_update_region(Thread * const user)
+	{
+		assert(user->pd_id() == core_id());
+
+		/* FIXME we don't handle instruction caches by now */
+		Cpu::flush_data_cache_by_virt_region((addr_t)user->user_arg_1(),
+		                                     (size_t)user->user_arg_2());
+	}
+
+
 	/**
 	 * Do specific syscall for 'user', for details see 'syscall.h'
 	 */
@@ -1372,6 +1385,7 @@ namespace Kernel
 			/* 29         */ do_ack_signal,
 			/* 30         */ do_kill_signal_context,
 			/* 31         */ do_pause_vm,
+			/* 32         */ do_update_region,
 		};
 		enum { MAX_SYSCALL = sizeof(handle_sysc)/sizeof(handle_sysc[0]) - 1 };
 

base-hw/src/core/ram_session_support.cc

@@ -13,6 +13,7 @@
 
 /* Genode includes */
 #include <base/printf.h>
+#include <kernel/syscalls.h>
 
 /* core includes */
 #include <ram_session_component.h>
@@ -27,5 +28,10 @@ void Ram_session_component::_revoke_ram_ds(Dataspace_component *ds) { }
 
 
 void Ram_session_component::_clear_ds (Dataspace_component * ds)
-{ memset((void *)ds->phys_addr(), 0, ds->size()); }
+{
+	memset((void *)ds->phys_addr(), 0, ds->size());
+
+	/* make the new DS-content visible to other PDs */
+	Kernel::update_region(ds->phys_addr(), ds->size());
+}
 

base/include/platform/arndale/drivers/board_base.h

@@ -49,7 +49,10 @@ namespace Genode
 			MCT_CLOCK     = 24000000,
 			MCT_IRQ_L0    = 152,
 
-			/* if board provides security extension */
+			/* CPU cache */
+			CACHE_LINE_SIZE_LOG2 = 6,
+
+			/* wether board provides security extension */
 			SECURITY_EXTENSION = 1,
 		};
 	};

base/include/platform/imx31/drivers/board_base.h

@@ -52,6 +52,9 @@ namespace Genode
 
 			AIPS_2_MMIO_BASE = 0x53F00000,
 			AIPS_2_MMIO_SIZE = 0x00004000,
+
+			/* CPU cache */
+			CACHE_LINE_SIZE_LOG2 = 2, /* FIXME get correct value from board spec */
 		};
 	};
 }

base/include/platform/imx53/drivers/board_base.h

@@ -103,7 +103,11 @@ namespace Genode
 			IIM_BASE           = 0x63f98000,
 			IIM_SIZE           = 0x00004000,
 
+			/* wether board provides security extension */
 			SECURITY_EXTENSION = 1,
+
+			/* CPU cache */
+			CACHE_LINE_SIZE_LOG2 = 2, /* FIXME get correct value from board spec */
 		};
 	};
 }

base/include/platform/panda/drivers/board_base.h

@@ -35,6 +35,7 @@ namespace Genode
 
 			/* clocks */
 			MPU_DPLL_CLOCK = 200*1000*1000,
+			SYS_CLK        = 38400000,
 
 			/* UARTs */
 			TL16C750_1_MMIO_BASE = MMIO_0_BASE + 0x6a000,
@@ -83,9 +84,12 @@ namespace Genode
 			GPIO6_MMIO_SIZE = 0x1000,
 			GPIO6_IRQ       = 34 + 32,
 
-			/* misc */
+			/* CPU cache */
+			CACHE_LINE_SIZE_LOG2 = 2, /* FIXME get correct value from board spec */
+
+			/* wether board provides security extension */
 			SECURITY_EXTENSION = 0,
-			SYS_CLK            = 38400000,
+
 		};
 	};
 }

base/include/platform/pbxa9/drivers/board_base.h

@@ -63,6 +63,10 @@ namespace Genode
 			SP804_0_1_IRQ       = 36,
 			SP804_0_1_CLOCK     = 1000*1000,
 
+			/* CPU cache */
+			CACHE_LINE_SIZE_LOG2 = 2, /* FIXME get correct value from board spec */
+
+			/* wether board provides security extension */
 			SECURITY_EXTENSION = 0,
 		};
 	};

base/include/platform/vea9x4/drivers/board_base.h

@@ -69,7 +69,11 @@ namespace Genode
 			CORTEX_A9_PRIVATE_MEM_SIZE = 0x2000,
 			CORTEX_A9_CLOCK = TCREF_CLOCK,
 
+			/* wether board provides security extension */
 			SECURITY_EXTENSION = 1,
+
+			/* CPU cache */
+			CACHE_LINE_SIZE_LOG2 = 2, /* FIXME get correct value from board spec */
 		};
 	};
 }