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77 lines
1.6 KiB
C++
77 lines
1.6 KiB
C++
/**
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* \brief Driver for the Realview PBXA9 board
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* \author Martin stein
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* \date 2011-11-03
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*/
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/*
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* Copyright (C) 2011-2013 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _INCLUDE__DRIVERS__BOARD_BASE_H_
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#define _INCLUDE__DRIVERS__BOARD_BASE_H_
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namespace Genode
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{
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/**
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* Driver for the Realview PBXA9 board
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*/
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struct Board_base
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{
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enum
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{
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/* normal RAM */
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RAM_0_BASE = 0x00000000,
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RAM_0_SIZE = 0x10000000,
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RAM_1_BASE = 0x20000000,
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RAM_1_SIZE = 0x10000000,
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/* device IO memory */
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MMIO_0_BASE = 0x10000000,
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MMIO_0_SIZE = 0x10000000,
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MMIO_1_BASE = 0x4e000000,
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MMIO_1_SIZE = 0x01000000,
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NORTHBRIDGE_AHB_BASE = 0x10020000,
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NORTHBRIDGE_AHB_SIZE = 768*1024,
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/* southbridge */
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SOUTHBRIDGE_APB_BASE = 0x10000000,
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SOUTHBRIDGE_APB_SIZE = 128*1024,
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/* clocks */
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OSC_6_CLOCK = 24*1000*1000,
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OSC_7_CLOCK = 14*1000*1000,
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/* CPU */
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CORTEX_A9_CLOCK = OSC_7_CLOCK * 5,
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CORTEX_A9_PRIVATE_MEM_BASE = 0x1f000000,
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CORTEX_A9_PRIVATE_MEM_SIZE = 0x01000000,
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/* UART */
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PL011_0_MMIO_BASE = 0x10009000,
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PL011_0_MMIO_SIZE = 0x00001000,
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PL011_0_CLOCK = OSC_6_CLOCK,
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PL011_0_IRQ = 44,
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/* timer */
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SP804_0_1_MMIO_BASE = 0x10011000,
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SP804_0_1_MMIO_SIZE = 0x00001000,
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SP804_0_1_IRQ = 36,
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SP804_0_1_CLOCK = 1000*1000,
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/* CPU cache */
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CACHE_LINE_SIZE_LOG2 = 2, /* FIXME get correct value from board spec */
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/* wether board provides security extension */
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SECURITY_EXTENSION = 0,
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};
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};
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}
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#endif /* _INCLUDE__DRIVERS__BOARD_BASE_H_ */
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