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pci_decode: report pci bridge configuration

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as setup by firmware after boot. The information will/can be used by the
platform driver to re-program bridges after a system suspend/resume cycle.

Issue #5241
This commit is contained in:
Alexander Boettcher 2024-06-06 10:41:49 +02:00 committed by Norman Feske
parent 7f152ea9ba
commit 0c97c13562
1 changed files with 23 additions and 1 deletions
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24
repos/os/src/app/pci_decode/main.cc
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@ -160,6 +160,7 @@ bus_t Main::parse_pci_function(Bdf bdf,
{
using C = Config;
using C0 = Config_type0;
using C1 = Config_type1;
using Cc = Config::Class_code_rev_id;
gen.attribute("address", string(cfg_phys_base));
@ -171,7 +172,28 @@ bus_t Main::parse_pci_function(Bdf bdf,
gen.attribute("class", string(cfg.read<Cc::Class_code>()));
gen.attribute("revision", string(cfg.read<Cc::Revision>()));
gen.attribute("bridge", cfg.bridge() ? "yes" : "no");
if (!cfg.bridge()) {
if (cfg.bridge()) {
C1 cfg1(cfg.range());
gen.attribute("io_base_limit",
string(cfg1.read<C1::Io_base_limit>()));
gen.attribute("memory_base",
string(cfg1.read<C1::Memory_base>()));
gen.attribute("memory_limit",
string(cfg1.read<C1::Memory_limit>()));
gen.attribute("prefetch_memory_base",
string(cfg1.read<C1::Prefetchable_memory_base>()));
gen.attribute("prefetch_memory_base_upper",
string(cfg1.read<C1::Prefetchable_memory_base_upper>()));
gen.attribute("prefetch_memory_limit_upper",
string(cfg1.read<C1::Prefetchable_memory_limit_upper>()));
gen.attribute("io_base_limit_upper",
string(cfg1.read<C1::Io_base_limit_upper>()));
gen.attribute("expansion_rom_base",
string(cfg1.read<C1::Expansion_rom_base_addr>()));
gen.attribute("bridge_control",
string(cfg1.read<C1::Bridge_control>()));
} else {
C0 cfg0(cfg.range());
gen.attribute("sub_vendor_id",
string(cfg0.read<C0::Subsystem_vendor>()));