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hw: catch all cache lines for mis-aligned addresses
Fix genodelabs/genode#4905
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@ -115,12 +115,7 @@ static inline void cache_maintainance(addr_t const base,
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size_t const cache_line_size,
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FUNC & func)
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{
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/**
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* Although, the ARMv7 reference manual states that addresses does not
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* need to be cacheline aligned, we observed problems when not doing so
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* on i.MX6 Quad Sabrelite (maybe Cortex A9 generic issue?).
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* Therefore, we align it here.
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*/
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/* align the start address to catch all related cache lines */
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addr_t start = base & ~(cache_line_size-1);
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addr_t const end = base + size;
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@ -95,7 +95,8 @@ static inline void cache_maintainance(addr_t const base,
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size_t const size,
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FUNC & func)
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{
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addr_t start = (addr_t) base;
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/* align the start address to catch all related cache lines */
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addr_t start = (addr_t)base & ~(Cpu::cache_line_size()-1UL);
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addr_t const end = base + size;
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for (; start < end; start += Cpu::cache_line_size()) func(start);
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}
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@ -45,7 +45,8 @@ static inline void for_each_cache_line(Genode::addr_t addr,
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static size_t cache_line_size = Kernel::cache_line_size();
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addr_t start = addr;
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/* align the start address to catch all related cache lines */
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addr_t start = addr & ~(cache_line_size-1);
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addr_t const end = addr + size;
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for (; start < end; start += cache_line_size)
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fn(start);
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