From 0aef0959d51611e2a183fdec60d594f1899d4f65 Mon Sep 17 00:00:00 2001 From: Stefan Kalkowski Date: Wed, 24 May 2023 13:44:08 +0200 Subject: [PATCH] hw: catch all cache lines for mis-aligned addresses Fix genodelabs/genode#4905 --- repos/base-hw/src/core/spec/arm/cpu.cc | 7 +------ repos/base-hw/src/core/spec/arm_v8/cpu.cc | 3 ++- repos/base-hw/src/include/base/internal/cache.h | 3 ++- 3 files changed, 5 insertions(+), 8 deletions(-) diff --git a/repos/base-hw/src/core/spec/arm/cpu.cc b/repos/base-hw/src/core/spec/arm/cpu.cc index e30604871a..b38b877d5b 100644 --- a/repos/base-hw/src/core/spec/arm/cpu.cc +++ b/repos/base-hw/src/core/spec/arm/cpu.cc @@ -115,12 +115,7 @@ static inline void cache_maintainance(addr_t const base, size_t const cache_line_size, FUNC & func) { - /** - * Although, the ARMv7 reference manual states that addresses does not - * need to be cacheline aligned, we observed problems when not doing so - * on i.MX6 Quad Sabrelite (maybe Cortex A9 generic issue?). - * Therefore, we align it here. - */ + /* align the start address to catch all related cache lines */ addr_t start = base & ~(cache_line_size-1); addr_t const end = base + size; diff --git a/repos/base-hw/src/core/spec/arm_v8/cpu.cc b/repos/base-hw/src/core/spec/arm_v8/cpu.cc index 7db1cd9bdb..d8ab97df57 100644 --- a/repos/base-hw/src/core/spec/arm_v8/cpu.cc +++ b/repos/base-hw/src/core/spec/arm_v8/cpu.cc @@ -95,7 +95,8 @@ static inline void cache_maintainance(addr_t const base, size_t const size, FUNC & func) { - addr_t start = (addr_t) base; + /* align the start address to catch all related cache lines */ + addr_t start = (addr_t)base & ~(Cpu::cache_line_size()-1UL); addr_t const end = base + size; for (; start < end; start += Cpu::cache_line_size()) func(start); } diff --git a/repos/base-hw/src/include/base/internal/cache.h b/repos/base-hw/src/include/base/internal/cache.h index 327db162d7..54a3752f53 100644 --- a/repos/base-hw/src/include/base/internal/cache.h +++ b/repos/base-hw/src/include/base/internal/cache.h @@ -45,7 +45,8 @@ static inline void for_each_cache_line(Genode::addr_t addr, static size_t cache_line_size = Kernel::cache_line_size(); - addr_t start = addr; + /* align the start address to catch all related cache lines */ + addr_t start = addr & ~(cache_line_size-1); addr_t const end = addr + size; for (; start < end; start += cache_line_size) fn(start);