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hw: catch all cache lines for mis-aligned addresses

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Fix genodelabs/genode#4905
This commit is contained in:
Stefan Kalkowski 2023-05-24 13:44:08 +02:00 committed by Christian Helmuth
parent 6b2338257d
commit 0aef0959d5
3 changed files with 5 additions and 8 deletions
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7
repos/base-hw/src/core/spec/arm/cpu.cc
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@ -115,12 +115,7 @@ static inline void cache_maintainance(addr_t const base,
size_t const cache_line_size, size_t const cache_line_size,
FUNC & func) FUNC & func)
{ {
/** /* align the start address to catch all related cache lines */
* Although, the ARMv7 reference manual states that addresses does not
* need to be cacheline aligned, we observed problems when not doing so
* on i.MX6 Quad Sabrelite (maybe Cortex A9 generic issue?).
* Therefore, we align it here.
*/
addr_t start = base & ~(cache_line_size-1); addr_t start = base & ~(cache_line_size-1);
addr_t const end = base + size; addr_t const end = base + size;

3
repos/base-hw/src/core/spec/arm_v8/cpu.cc
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@ -95,7 +95,8 @@ static inline void cache_maintainance(addr_t const base,
size_t const size, size_t const size,
FUNC & func) FUNC & func)
{ {
addr_t start = (addr_t) base; /* align the start address to catch all related cache lines */
addr_t start = (addr_t)base & ~(Cpu::cache_line_size()-1UL);
addr_t const end = base + size; addr_t const end = base + size;
for (; start < end; start += Cpu::cache_line_size()) func(start); for (; start < end; start += Cpu::cache_line_size()) func(start);
} }

3
repos/base-hw/src/include/base/internal/cache.h
View File

@ -45,7 +45,8 @@ static inline void for_each_cache_line(Genode::addr_t addr,
static size_t cache_line_size = Kernel::cache_line_size(); static size_t cache_line_size = Kernel::cache_line_size();
addr_t start = addr; /* align the start address to catch all related cache lines */
addr_t start = addr & ~(cache_line_size-1);
addr_t const end = addr + size; addr_t const end = addr + size;
for (; start < end; start += cache_line_size) for (; start < end; start += cache_line_size)
fn(start); fn(start);