mirror of
https://github.com/genodelabs/genode.git
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base-hw: global IRQ controller as Main member
Let the kernel's driver for the global IRQ controller be a member of the one Kernel::Main object instead of having it as static variables in the drivers for the local IRQ controllers. Note that this commit spares out renaming 'Pic' to 'Local_interrupt_controller' which would be more sensible now with the new 'Global_interrupt_controller' class. Furthermore, on ARM boards the commit doesn't move 'Distributer' stuff to the new global IRQ controller class as they don't have real data members (only MMIO) and can be instanciated for each CPU anew. However, the right way would be to instanciate them only once in Main as well. Ref #4217
This commit is contained in:
Martin Stein
Norman Feske
parent
441d137482
commit
02f00a999c
@ -26,7 +26,8 @@ namespace Board {
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using namespace Hw::Imx6q_sabrelite_board;
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class Pic : public Hw::Gicv2 { };
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class Global_interrupt_controller { };
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class Pic : public Hw::Gicv2 { public: Pic(Global_interrupt_controller &) { } };
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using L2_cache = Hw::Pl310;
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@ -26,7 +26,8 @@ namespace Board {
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using namespace Hw::Nit6_solox_board;
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class Pic : public Hw::Gicv2 { };
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class Global_interrupt_controller { };
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class Pic : public Hw::Gicv2 { public: Pic(Global_interrupt_controller &) { } };
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using L2_cache = Hw::Pl310;
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@ -26,7 +26,8 @@ namespace Board {
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using namespace Hw::Pbxa9_board;
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class Pic : public Hw::Gicv2 { };
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class Global_interrupt_controller { };
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class Pic : public Hw::Gicv2 { public: Pic(Global_interrupt_controller &) { } };
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L2_cache & l2_cache();
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}
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@ -26,6 +26,8 @@ namespace Board {
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using namespace Hw::Pc_board;
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class Pic : public Local_interrupt_controller { };
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enum {
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VECTOR_REMAP_BASE = 48,
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TIMER_VECTOR_KERNEL = 32,
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@ -29,7 +29,8 @@ namespace Board {
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using L2_cache = Hw::Pl310;
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class Pic : public Hw::Gicv2 { };
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class Global_interrupt_controller { };
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class Pic : public Hw::Gicv2 { public: Pic(Global_interrupt_controller &) { } };
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L2_cache & l2_cache();
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@ -28,7 +28,8 @@ namespace Board {
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using namespace Hw::Zynq_qemu_board;
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class Pic : public Hw::Gicv2 { };
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class Global_interrupt_controller { };
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class Pic : public Hw::Gicv2 { public: Pic(Global_interrupt_controller &) { } };
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L2_cache & l2_cache();
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}
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@ -174,13 +174,15 @@ addr_t Cpu::stack_start()
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}
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Cpu::Cpu(unsigned const id,
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Board::Address_space_id_allocator &addr_space_id_alloc,
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Irq::Pool &user_irq_pool,
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Cpu_pool &cpu_pool,
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Pd &core_pd)
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Cpu::Cpu(unsigned const id,
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Board::Address_space_id_allocator &addr_space_id_alloc,
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Irq::Pool &user_irq_pool,
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Cpu_pool &cpu_pool,
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Pd &core_pd,
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Board::Global_interrupt_controller &global_irq_ctrl)
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:
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_id { id },
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_pic { global_irq_ctrl },
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_timer { *this },
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_scheduler { _idle, _quota(), _fill() },
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_idle { addr_space_id_alloc, user_irq_pool, cpu_pool, *this,
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@ -198,13 +200,14 @@ Cpu::Cpu(unsigned const id,
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void
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Cpu_pool::
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initialize_executing_cpu(Board::Address_space_id_allocator &addr_space_id_alloc,
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Irq::Pool &user_irq_pool,
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Pd &core_pd)
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initialize_executing_cpu(Board::Address_space_id_allocator &addr_space_id_alloc,
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Irq::Pool &user_irq_pool,
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Pd &core_pd,
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Board::Global_interrupt_controller &global_irq_ctrl)
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{
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unsigned id = Cpu::executing_id();
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_cpus[id].construct(
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id, addr_space_id_alloc, user_irq_pool, *this, core_pd);
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id, addr_space_id_alloc, user_irq_pool, *this, core_pd, global_irq_ctrl);
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}
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@ -111,7 +111,7 @@ class Kernel::Cpu : public Genode::Cpu, private Irq::Pool, private Timeout
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unsigned const _id;
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Board::Pic _pic {};
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Board::Pic _pic;
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Timer _timer;
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Cpu_scheduler _scheduler;
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Idle_thread _idle;
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@ -131,11 +131,12 @@ class Kernel::Cpu : public Genode::Cpu, private Irq::Pool, private Timeout
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/**
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* Construct object for CPU 'id'
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*/
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Cpu(unsigned const id,
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Board::Address_space_id_allocator &addr_space_id_alloc,
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Irq::Pool &user_irq_pool,
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Cpu_pool &cpu_pool,
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Pd &core_pd);
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Cpu(unsigned const id,
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Board::Address_space_id_allocator &addr_space_id_alloc,
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Irq::Pool &user_irq_pool,
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Cpu_pool &cpu_pool,
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Pd &core_pd,
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Board::Global_interrupt_controller &global_irq_ctrl);
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static inline unsigned primary_id() { return 0; }
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@ -207,9 +208,10 @@ class Kernel::Cpu_pool
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Cpu_pool(unsigned nr_of_cpus);
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void
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initialize_executing_cpu(Board::Address_space_id_allocator &addr_space_id_alloc,
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Irq::Pool &user_irq_pool,
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Pd &core_pd);
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initialize_executing_cpu(Board::Address_space_id_allocator &addr_space_id_alloc,
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Irq::Pool &user_irq_pool,
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Pd &core_pd,
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Board::Global_interrupt_controller &global_irq_ctrl);
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/**
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* Return object of CPU 'id'
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@ -51,6 +51,7 @@ class Kernel::Main
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Board::Address_space_id_allocator _addr_space_id_alloc { };
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Genode::Core_platform_pd _core_platform_pd { _addr_space_id_alloc };
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Genode::Constructible<Core_main_thread> _core_main_thread { };
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Board::Global_interrupt_controller _global_irq_ctrl { };
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void _handle_kernel_entry();
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@ -137,7 +138,8 @@ void Kernel::main_initialize_and_handle_kernel_entry()
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Main::_instance->_cpu_pool.initialize_executing_cpu(
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Main::_instance->_addr_space_id_alloc,
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Main::_instance->_user_irq_pool,
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Main::_instance->_core_platform_pd.kernel_pd());
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Main::_instance->_core_platform_pd.kernel_pd(),
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Main::_instance->_global_irq_ctrl);
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nr_of_initialized_cpus++;
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};
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@ -37,9 +37,11 @@ bool Board::Pic::Usb_dwc_otg::_need_trigger_sof(uint32_t host_frame,
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}
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Board::Pic::Usb_dwc_otg::Usb_dwc_otg()
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Board::Pic::
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Usb_dwc_otg::Usb_dwc_otg(Global_interrupt_controller &global_irq_ctrl)
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:
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Mmio(Platform::mmio_to_virt(Board::USB_DWC_OTG_BASE))
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Mmio { Platform::mmio_to_virt(Board::USB_DWC_OTG_BASE) },
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_global_irq_ctrl { global_irq_ctrl }
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{
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write<Guid::Num>(0);
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write<Guid::Num_valid>(false);
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@ -52,10 +54,8 @@ bool Board::Pic::Usb_dwc_otg::handle_sof()
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if (!_is_sof())
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return false;
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static int cnt = 0;
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if (++cnt == 8*20) {
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cnt = 0;
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if (_global_irq_ctrl.increment_and_return_sof_cnt() == 8*20) {
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_global_irq_ctrl.reset_sof_cnt();
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return false;
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}
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@ -72,9 +72,10 @@ bool Board::Pic::Usb_dwc_otg::handle_sof()
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}
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Board::Pic::Pic()
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Board::Pic::Pic(Global_interrupt_controller &global_irq_ctrl)
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:
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Mmio(Platform::mmio_to_virt(Board::IRQ_CONTROLLER_BASE))
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Mmio { Platform::mmio_to_virt(Board::IRQ_CONTROLLER_BASE) },
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_usb { global_irq_ctrl }
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{
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mask();
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}
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@ -17,7 +17,25 @@
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/* Genode includes */
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#include <util/mmio.h>
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namespace Board { class Pic; }
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namespace Board {
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class Global_interrupt_controller;
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class Pic;
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}
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class Board::Global_interrupt_controller
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{
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private:
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int _sof_cnt { 0 };
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public:
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int increment_and_return_sof_cnt() { return ++_sof_cnt; }
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void reset_sof_cnt() { _sof_cnt = 0; }
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};
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class Board::Pic : Genode::Mmio
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@ -80,6 +98,8 @@ class Board::Pic : Genode::Mmio
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struct Num : Bitfield<0, 14> { };
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};
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Global_interrupt_controller &_global_irq_ctrl;
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bool _is_sof() const
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{
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return read<Core_irq_status::Sof>();
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@ -90,12 +110,12 @@ class Board::Pic : Genode::Mmio
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public:
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Usb_dwc_otg();
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Usb_dwc_otg(Global_interrupt_controller &global_irq_ctrl);
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bool handle_sof();
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};
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Usb_dwc_otg _usb { };
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Usb_dwc_otg _usb;
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/**
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* Return true if specified interrupt is pending
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@ -108,7 +128,7 @@ class Board::Pic : Genode::Mmio
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public:
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Pic();
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Pic(Global_interrupt_controller &global_irq_ctrl);
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bool take_request(unsigned &irq);
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void finish_request() { }
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@ -16,7 +16,7 @@
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#include <platform.h>
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Board::Pic::Pic()
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Board::Pic::Pic(Global_interrupt_controller &)
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:
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Genode::Mmio(Genode::Platform::mmio_to_virt(Board::LOCAL_IRQ_CONTROLLER_BASE))
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{ }
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@ -16,7 +16,11 @@
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#include <util/mmio.h>
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namespace Board { class Pic; }
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namespace Board {
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class Global_interrupt_controller { };
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class Pic;
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}
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class Board::Pic : Genode::Mmio
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@ -54,7 +58,7 @@ class Board::Pic : Genode::Mmio
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public:
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Pic();
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Pic(Global_interrupt_controller &);
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bool take_request(unsigned &irq);
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void finish_request() { }
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@ -27,7 +27,8 @@ namespace Board {
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struct Vm_page_table {};
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struct Vm_page_table_array {};
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struct Pic : Hw::Pic { struct Virtual_context {}; };
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class Global_interrupt_controller { };
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struct Pic : Hw::Pic { struct Virtual_context {}; Pic(Global_interrupt_controller &) { } };
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struct Vcpu_context { Vcpu_context(Kernel::Cpu &) {} };
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}
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@ -16,7 +16,11 @@
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#include <hw/spec/arm/gicv2.h>
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namespace Board { struct Pic; };
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namespace Board {
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class Global_interrupt_controller { };
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class Pic;
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};
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class Board::Pic : public Hw::Gicv2
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@ -50,6 +54,8 @@ class Board::Pic : public Hw::Gicv2
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bool ack_virtual_irq(Virtual_context & c);
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void insert_virtual_irq(Virtual_context & c, unsigned irq);
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Pic(Global_interrupt_controller &) { }
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};
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#endif /* _CORE__SPEC__ARM__VIRTUALIZATION__GICV2_H_ */
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@ -16,7 +16,11 @@
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#include <hw/spec/arm/gicv3.h>
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namespace Board { class Pic; };
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namespace Board {
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class Global_interrupt_controller { };
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class Pic;
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};
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class Board::Pic : public Hw::Pic
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@ -51,6 +55,8 @@ class Board::Pic : public Hw::Pic
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c.lr = irq | 1ULL << 41 | 1ULL << 60 | 1ULL << 62;
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}
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Pic(Global_interrupt_controller &) { }
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};
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#endif /* _CORE__SPEC__ARM__VIRTUALIZATION__GICV3_H_ */
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@ -16,7 +16,8 @@
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#include <pic.h>
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#include <platform.h>
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Board::Pic::Pic() :
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Board::Pic::Pic(Global_interrupt_controller &)
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:
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_plic(Genode::Platform::mmio_to_virt(Board::PLIC_BASE))
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{
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/* enable external interrupts */
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@ -20,7 +20,11 @@
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#include <util/mmio.h>
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#include <plic.h>
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namespace Board { class Pic; }
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namespace Board {
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class Global_interrupt_controller { };
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class Pic;
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}
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/**
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@ -44,7 +48,7 @@ class Board::Pic
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NR_OF_IRQ = Plic::NR_OF_IRQ,
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};
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Pic();
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Pic(Global_interrupt_controller &);
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bool take_request(unsigned & irq)
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{
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@ -24,11 +24,8 @@
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using namespace Genode;
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using namespace Board;
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uint8_t Pic::lapic_ids[NR_OF_CPUS];
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enum {
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REMAP_BASE = Board::VECTOR_REMAP_BASE,
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PIC_CMD_MASTER = 0x20,
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PIC_CMD_SLAVE = 0xa0,
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PIC_DATA_MASTER = 0x21,
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@ -36,9 +33,15 @@ enum {
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};
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Pic::Pic()
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/***************************************
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** Board::Local_interrupt_controller **
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***************************************/
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Local_interrupt_controller::
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Local_interrupt_controller(Global_interrupt_controller &global_irq_ctrl)
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:
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Mmio(Platform::mmio_to_virt(Hw::Cpu_memory_map::lapic_phys_base()))
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Mmio { Platform::mmio_to_virt(Hw::Cpu_memory_map::lapic_phys_base()) },
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_global_irq_ctrl { global_irq_ctrl }
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{
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/* Start initialization sequence in cascade mode */
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outb(PIC_CMD_MASTER, 0x11);
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@ -68,7 +71,7 @@ Pic::Pic()
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}
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bool Pic::take_request(unsigned &irq)
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bool Local_interrupt_controller::take_request(unsigned &irq)
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{
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irq = get_lowest_bit();
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if (!irq) {
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@ -80,32 +83,33 @@ bool Pic::take_request(unsigned &irq)
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}
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void Pic::finish_request()
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void Local_interrupt_controller::finish_request()
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{
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write<EOI>(0);
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}
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void Pic::unmask(unsigned const i, unsigned)
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void Local_interrupt_controller::unmask(unsigned const i, unsigned)
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{
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ioapic.toggle_mask(i, false);
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_global_irq_ctrl.toggle_mask(i, false);
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}
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void Pic::mask(unsigned const i)
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void Local_interrupt_controller::mask(unsigned const i)
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{
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ioapic.toggle_mask(i, true);
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_global_irq_ctrl.toggle_mask(i, true);
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}
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void Pic::irq_mode(unsigned irq_number, unsigned trigger,
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unsigned polarity)
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void Local_interrupt_controller::irq_mode(unsigned irq_number,
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unsigned trigger,
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unsigned polarity)
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{
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ioapic.irq_mode(irq_number, trigger, polarity);
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_global_irq_ctrl.irq_mode(irq_number, trigger, polarity);
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}
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inline unsigned Pic::get_lowest_bit(void)
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inline unsigned Local_interrupt_controller::get_lowest_bit()
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{
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unsigned bit, vec_base = 0;
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@ -120,7 +124,7 @@ inline unsigned Pic::get_lowest_bit(void)
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}
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void Pic::send_ipi(unsigned const cpu_id)
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void Local_interrupt_controller::send_ipi(unsigned const cpu_id)
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{
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while (read<Icr_low::Delivery_status>())
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asm volatile("pause" : : : "memory");
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@ -128,9 +132,9 @@ void Pic::send_ipi(unsigned const cpu_id)
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Icr_high::access_t icr_high = 0;
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Icr_low::access_t icr_low = 0;
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Icr_high::Destination::set(icr_high, lapic_ids[cpu_id]);
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Icr_high::Destination::set(icr_high, _global_irq_ctrl.lapic_id(cpu_id));
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Icr_low::Vector::set(icr_low, Pic::IPI);
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Icr_low::Vector::set(icr_low, Local_interrupt_controller::IPI);
|
||||
Icr_low::Level_assert::set(icr_low);
|
||||
|
||||
/* program */
|
||||
@ -139,14 +143,26 @@ void Pic::send_ipi(unsigned const cpu_id)
|
||||
}
|
||||
|
||||
|
||||
Ioapic::Irq_mode Ioapic::_irq_mode[IRQ_COUNT];
|
||||
/****************************************
|
||||
** Board::Global_interrupt_controller **
|
||||
****************************************/
|
||||
|
||||
uint8_t Global_interrupt_controller::lapic_id(unsigned cpu_id) const
|
||||
{
|
||||
return _lapic_id[cpu_id];
|
||||
}
|
||||
|
||||
|
||||
enum { REMAP_BASE = Board::VECTOR_REMAP_BASE };
|
||||
void Global_interrupt_controller::lapic_id(unsigned cpu_id,
|
||||
uint8_t lapic_id)
|
||||
{
|
||||
_lapic_id[cpu_id] = lapic_id;
|
||||
}
|
||||
|
||||
|
||||
void Ioapic::irq_mode(unsigned irq_number, unsigned trigger,
|
||||
unsigned polarity)
|
||||
void Global_interrupt_controller::irq_mode(unsigned irq_number,
|
||||
unsigned trigger,
|
||||
unsigned polarity)
|
||||
{
|
||||
const unsigned irq_nr = irq_number - REMAP_BASE;
|
||||
bool needs_sync = false;
|
||||
@ -185,7 +201,7 @@ void Ioapic::irq_mode(unsigned irq_number, unsigned trigger,
|
||||
}
|
||||
|
||||
|
||||
void Ioapic::_update_irt_entry(unsigned irq)
|
||||
void Global_interrupt_controller::_update_irt_entry(unsigned irq)
|
||||
{
|
||||
Irte::access_t irte;
|
||||
|
||||
@ -200,7 +216,8 @@ void Ioapic::_update_irt_entry(unsigned irq)
|
||||
}
|
||||
|
||||
|
||||
Irte::access_t Ioapic::_create_irt_entry(unsigned const irq)
|
||||
Irte::access_t
|
||||
Global_interrupt_controller::_create_irt_entry(unsigned const irq)
|
||||
{
|
||||
Irte::access_t irte = REMAP_BASE + irq;
|
||||
Irte::Mask::set(irte, 1);
|
||||
@ -212,7 +229,7 @@ Irte::access_t Ioapic::_create_irt_entry(unsigned const irq)
|
||||
}
|
||||
|
||||
|
||||
Ioapic::Ioapic()
|
||||
Global_interrupt_controller::Global_interrupt_controller()
|
||||
:
|
||||
Mmio(Platform::mmio_to_virt(Hw::Cpu_memory_map::MMIO_IOAPIC_BASE))
|
||||
{
|
||||
@ -242,7 +259,8 @@ Ioapic::Ioapic()
|
||||
};
|
||||
|
||||
|
||||
void Ioapic::toggle_mask(unsigned const vector, bool const set)
|
||||
void Global_interrupt_controller::toggle_mask(unsigned const vector,
|
||||
bool const set)
|
||||
{
|
||||
/*
|
||||
* Ignore toggle requests for vectors not handled by the I/O APIC.
|
||||
|
||||
@ -18,9 +18,6 @@
|
||||
/* Genode includes */
|
||||
#include <util/mmio.h>
|
||||
|
||||
/* core includes */
|
||||
#include <board.h>
|
||||
|
||||
namespace Board {
|
||||
|
||||
/*
|
||||
@ -31,12 +28,12 @@ namespace Board {
|
||||
/**
|
||||
* IO advanced programmable interrupt controller
|
||||
*/
|
||||
class Ioapic;
|
||||
class Global_interrupt_controller;
|
||||
|
||||
/**
|
||||
* Programmable interrupt controller for core
|
||||
*/
|
||||
class Pic;
|
||||
class Local_interrupt_controller;
|
||||
|
||||
enum { IRQ_COUNT = 256 };
|
||||
}
|
||||
@ -50,13 +47,10 @@ struct Board::Irte : Genode::Register<64>
|
||||
};
|
||||
|
||||
|
||||
class Board::Ioapic : public Genode::Mmio
|
||||
class Board::Global_interrupt_controller : public Genode::Mmio
|
||||
{
|
||||
private:
|
||||
|
||||
/* Number of Redirection Table entries */
|
||||
unsigned _irte_count = 0;
|
||||
|
||||
enum {
|
||||
/* Register selectors */
|
||||
IOAPICVER = 0x01,
|
||||
@ -78,7 +72,19 @@ class Board::Ioapic : public Genode::Mmio
|
||||
unsigned polarity;
|
||||
};
|
||||
|
||||
static Irq_mode _irq_mode[IRQ_COUNT];
|
||||
/*
|
||||
* Registers
|
||||
*/
|
||||
|
||||
struct Ioregsel : Register<0x00, 32> { };
|
||||
struct Iowin : Register<0x10, 32>
|
||||
{
|
||||
struct Maximum_redirection_entry : Bitfield<16, 8> { };
|
||||
};
|
||||
|
||||
unsigned _irte_count = 0; /* number of redirection table entries */
|
||||
Genode::uint8_t _lapic_id[NR_OF_CPUS]; /* unique name of the LAPIC of each CPU */
|
||||
Irq_mode _irq_mode[IRQ_COUNT];
|
||||
|
||||
/**
|
||||
* Return whether 'irq' is an edge-triggered interrupt
|
||||
@ -104,7 +110,7 @@ class Board::Ioapic : public Genode::Mmio
|
||||
|
||||
public:
|
||||
|
||||
Ioapic();
|
||||
Global_interrupt_controller();
|
||||
|
||||
/**
|
||||
* Set/unset mask bit of IRTE for given vector
|
||||
@ -112,7 +118,8 @@ class Board::Ioapic : public Genode::Mmio
|
||||
* \param vector targeted vector
|
||||
* \param set whether to set or to unset the mask bit
|
||||
*/
|
||||
void toggle_mask(unsigned const vector, bool const set);
|
||||
void toggle_mask(unsigned const vector,
|
||||
bool const set);
|
||||
|
||||
/**
|
||||
* Setup mode of an IRQ to specified trigger mode and polarity
|
||||
@ -121,22 +128,23 @@ class Board::Ioapic : public Genode::Mmio
|
||||
* \param trigger new interrupt trigger mode
|
||||
* \param polarity new interrupt polarity setting
|
||||
*/
|
||||
void irq_mode(unsigned irq_number, unsigned trigger,
|
||||
void irq_mode(unsigned irq_number,
|
||||
unsigned trigger,
|
||||
unsigned polarity);
|
||||
|
||||
/*
|
||||
* Registers
|
||||
*/
|
||||
|
||||
struct Ioregsel : Register<0x00, 32> { };
|
||||
struct Iowin : Register<0x10, 32>
|
||||
{
|
||||
struct Maximum_redirection_entry : Bitfield<16, 8> { };
|
||||
};
|
||||
/***************
|
||||
** Accessors **
|
||||
***************/
|
||||
|
||||
void lapic_id(unsigned cpu_id,
|
||||
Genode::uint8_t lapic_id);
|
||||
|
||||
Genode::uint8_t lapic_id(unsigned cpu_id) const;
|
||||
};
|
||||
|
||||
|
||||
class Board::Pic : public Genode::Mmio
|
||||
class Board::Local_interrupt_controller : public Genode::Mmio
|
||||
{
|
||||
private:
|
||||
|
||||
@ -173,6 +181,8 @@ class Board::Pic : public Genode::Mmio
|
||||
struct Destination : Bitfield<24, 8> { };
|
||||
};
|
||||
|
||||
Global_interrupt_controller &_global_irq_ctrl;
|
||||
|
||||
/**
|
||||
* Determine lowest pending interrupt in ISR register
|
||||
*
|
||||
@ -181,11 +191,6 @@ class Board::Pic : public Genode::Mmio
|
||||
*/
|
||||
inline unsigned get_lowest_bit(void);
|
||||
|
||||
/**
|
||||
* Mapping of our logical boot CPUs to the local APIC IDs
|
||||
*/
|
||||
static Genode::uint8_t lapic_ids[NR_OF_CPUS];
|
||||
|
||||
public:
|
||||
|
||||
enum {
|
||||
@ -201,9 +206,7 @@ class Board::Pic : public Genode::Mmio
|
||||
/**
|
||||
* Constructor
|
||||
*/
|
||||
Pic();
|
||||
|
||||
Ioapic ioapic { };
|
||||
Local_interrupt_controller(Global_interrupt_controller &global_irq_ctrl);
|
||||
|
||||
bool take_request(unsigned &irq);
|
||||
|
||||
@ -219,7 +222,7 @@ class Board::Pic : public Genode::Mmio
|
||||
{
|
||||
if (cpu_id < NR_OF_CPUS) {
|
||||
Id::access_t const lapic_id = read<Id>();
|
||||
lapic_ids[cpu_id] = (lapic_id >> 24) & 0xff;
|
||||
_global_irq_ctrl.lapic_id(cpu_id, (lapic_id >> 24) & 0xff);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user