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genode/repos/base/include/drivers/defs/wand_quad.h

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hw: support Wandboard Quad (i.MX6) The port uses the Cortex-A9 private timer for the kernel and an EPIT as user timer. It was successfully tested on the Wandboard Quad and the CuBox-i with the signal test. It lacks L2-cache and Trustzone support by now. Thanks to Praveen Srinivas (IIT Madras, India) and Nikolay Golikov (Ksys Labs LLC, Russia). This work is partially based on their contributions. Fix #1467
2015-03-25 18:30:37 +00:00
/*
base: remove include/spec/* other than ISA This commit moves the headers residing in `repos/base/include/spec/*/drivers` to `repos/base/include/drivers/defs` or repos/base/include/drivers/uart` respectively. The first one contains definitions about board-specific MMIO iand RAM addresses, or IRQ lines. While the latter contains device driver code for UART devices. Those definitions are used by driver implementations in `repos/base-hw`, `repos/os`, and `repos/dde-linux`, which now need to include them more explicitely. This work is a step in the direction of reducing 'SPEC' identifiers overall. Ref #2403
2017-04-28 13:27:26 +00:00
* \brief MMIO and IRQ definitions of the Wandboard Quad
hw: support Wandboard Quad (i.MX6) The port uses the Cortex-A9 private timer for the kernel and an EPIT as user timer. It was successfully tested on the Wandboard Quad and the CuBox-i with the signal test. It lacks L2-cache and Trustzone support by now. Thanks to Praveen Srinivas (IIT Madras, India) and Nikolay Golikov (Ksys Labs LLC, Russia). This work is partially based on their contributions. Fix #1467
2015-03-25 18:30:37 +00:00
* \author Nikolay Golikov <nik@ksyslabs.org>
* \author Josef Soentgen
* \author Martin Stein
* \date 2014-02-25
*/
/*
hw: enable SMP for ARM Cortex A9 This commit enables multi-processing for all Cortex A9 SoCs we currently support. Moreover, it thereby enables the L2 cache for i.MX6 that was not enabled until now. However, the QEMU variants hw_pbxa9 and hw_zynq still only use 1 core, because the busy cpu synchronization used when initializing multiple Cortex A9 cores leads to horrible boot times on QEMU. During this work the CPU initialization in general was reworked. From now on lots of hardware specifics were put into the 'spec' specific files, some generic hook functions and abstractions thereby were eliminated. This results to more lean implementations for instance on non-SMP platforms, or in the x86 case where cache maintainance is a non-issue. Due to the fact that memory/cache coherency and SMP are closely coupled on ARM Cortex A9 this commit combines so different aspects. Fix #1312 Fix #1807
2016-01-11 10:02:52 +00:00
* Copyright (C) 2014-2016 Ksys Labs LLC
Adjust file headers to refer to the AGPLv3
2017-02-20 12:23:52 +00:00
* Copyright (C) 2014-2017 Genode Labs GmbH
hw: support Wandboard Quad (i.MX6) The port uses the Cortex-A9 private timer for the kernel and an EPIT as user timer. It was successfully tested on the Wandboard Quad and the CuBox-i with the signal test. It lacks L2-cache and Trustzone support by now. Thanks to Praveen Srinivas (IIT Madras, India) and Nikolay Golikov (Ksys Labs LLC, Russia). This work is partially based on their contributions. Fix #1467
2015-03-25 18:30:37 +00:00
*
* This file is part of the Genode OS framework, which is distributed
Adjust file headers to refer to the AGPLv3
2017-02-20 12:23:52 +00:00
* under the terms of the GNU Affero General Public License version 3.
hw: support Wandboard Quad (i.MX6) The port uses the Cortex-A9 private timer for the kernel and an EPIT as user timer. It was successfully tested on the Wandboard Quad and the CuBox-i with the signal test. It lacks L2-cache and Trustzone support by now. Thanks to Praveen Srinivas (IIT Madras, India) and Nikolay Golikov (Ksys Labs LLC, Russia). This work is partially based on their contributions. Fix #1467
2015-03-25 18:30:37 +00:00
*/
base: remove include/spec/* other than ISA This commit moves the headers residing in `repos/base/include/spec/*/drivers` to `repos/base/include/drivers/defs` or repos/base/include/drivers/uart` respectively. The first one contains definitions about board-specific MMIO iand RAM addresses, or IRQ lines. While the latter contains device driver code for UART devices. Those definitions are used by driver implementations in `repos/base-hw`, `repos/os`, and `repos/dde-linux`, which now need to include them more explicitely. This work is a step in the direction of reducing 'SPEC' identifiers overall. Ref #2403
2017-04-28 13:27:26 +00:00
#ifndef _INCLUDE__DRIVERS__DEFS__WAND_QUAD_H_
#define _INCLUDE__DRIVERS__DEFS__WAND_QUAD_H_
hw: support Wandboard Quad (i.MX6) The port uses the Cortex-A9 private timer for the kernel and an EPIT as user timer. It was successfully tested on the Wandboard Quad and the CuBox-i with the signal test. It lacks L2-cache and Trustzone support by now. Thanks to Praveen Srinivas (IIT Madras, India) and Nikolay Golikov (Ksys Labs LLC, Russia). This work is partially based on their contributions. Fix #1467
2015-03-25 18:30:37 +00:00
sd_card: move defs from wand_quad to imx6 header
2017-06-21 09:36:29 +00:00
/* Genode includes */
#include <drivers/defs/imx6.h>
base: remove include/spec/* other than ISA This commit moves the headers residing in `repos/base/include/spec/*/drivers` to `repos/base/include/drivers/defs` or repos/base/include/drivers/uart` respectively. The first one contains definitions about board-specific MMIO iand RAM addresses, or IRQ lines. While the latter contains device driver code for UART devices. Those definitions are used by driver implementations in `repos/base-hw`, `repos/os`, and `repos/dde-linux`, which now need to include them more explicitely. This work is a step in the direction of reducing 'SPEC' identifiers overall. Ref #2403
2017-04-28 13:27:26 +00:00
namespace Wand_quad {
sd_card: move defs from wand_quad to imx6 header
2017-06-21 09:36:29 +00:00
using namespace Imx6;
hw: support Wandboard Quad (i.MX6) The port uses the Cortex-A9 private timer for the kernel and an EPIT as user timer. It was successfully tested on the Wandboard Quad and the CuBox-i with the signal test. It lacks L2-cache and Trustzone support by now. Thanks to Praveen Srinivas (IIT Madras, India) and Nikolay Golikov (Ksys Labs LLC, Russia). This work is partially based on their contributions. Fix #1467
2015-03-25 18:30:37 +00:00
enum {
/* normal RAM */
RAM0_BASE = 0x10000000,
RAM0_SIZE = 0x80000000,
/* device IO memory */
MMIO_BASE = 0x00000000,
MMIO_SIZE = 0x10000000,
UART_1_IRQ = 58,
UART_1_MMIO_BASE = 0x02020000,
UART_1_MMIO_SIZE = 0x00004000,
/* timer */
EPIT_2_IRQ = 89,
EPIT_2_MMIO_BASE = 0x020d4000,
EPIT_2_MMIO_SIZE = 0x00004000,
/* ARM IP Bus control */
AIPS_1_MMIO_BASE = 0x0207c000,
AIPS_1_MMIO_SIZE = 0x00004000,
AIPS_2_MMIO_BASE = 0x0217c000,
AIPS_2_MMIO_SIZE = 0x00004000,
/* CPU */
CORTEX_A9_PRIVATE_MEM_BASE = 0x00a00000,
CORTEX_A9_PRIVATE_MEM_SIZE = 0x00002000,
CORTEX_A9_PRIVATE_TIMER_CLK = 395037500,
hw: use kernel timer for timer driver * Adds public timeout syscalls to kernel API * Kernel::timeout installs a timeout and binds a signal context to it that shall trigger once the timeout expired * With Kernel::timeout_max_us, one can get the maximum installable timeout * Kernel::timeout_age_us returns the time that has passed since the calling threads last timeout installation * Removes all device specific back-ends for the base-hw timer driver and implements a generic back-end taht uses the kernel timeout API * Adds assertions about the kernel timer frequency that originate from the requirements of the the kernel timeout API and adjusts all timers accordingly by using the their internal dividers * Introduces the Kernel::Clock class. As member of each Kernel::Cpu object it combines the management of the timer of the CPU with a timeout scheduler. Not only the timeout API uses the timeout scheduler but also the CPUs job scheduler for installing scheduling timeouts. * Introduces the Kernel::time_t type for timer tic values and values inherited from timer tics (like microseconds). Fixes #1972
2016-05-18 10:20:04 +00:00
CORTEX_A9_PRIVATE_TIMER_DIV = 170,
hw: support Wandboard Quad (i.MX6) The port uses the Cortex-A9 private timer for the kernel and an EPIT as user timer. It was successfully tested on the Wandboard Quad and the CuBox-i with the signal test. It lacks L2-cache and Trustzone support by now. Thanks to Praveen Srinivas (IIT Madras, India) and Nikolay Golikov (Ksys Labs LLC, Russia). This work is partially based on their contributions. Fix #1467
2015-03-25 18:30:37 +00:00
hw: enable SMP for ARM Cortex A9 This commit enables multi-processing for all Cortex A9 SoCs we currently support. Moreover, it thereby enables the L2 cache for i.MX6 that was not enabled until now. However, the QEMU variants hw_pbxa9 and hw_zynq still only use 1 core, because the busy cpu synchronization used when initializing multiple Cortex A9 cores leads to horrible boot times on QEMU. During this work the CPU initialization in general was reworked. From now on lots of hardware specifics were put into the 'spec' specific files, some generic hook functions and abstractions thereby were eliminated. This results to more lean implementations for instance on non-SMP platforms, or in the x86 case where cache maintainance is a non-issue. Due to the fact that memory/cache coherency and SMP are closely coupled on ARM Cortex A9 this commit combines so different aspects. Fix #1312 Fix #1807
2016-01-11 10:02:52 +00:00
/* L2 cache controller */
PL310_MMIO_BASE = 0x00a02000,
PL310_MMIO_SIZE = 0x00001000,
hw: enable SMP for Wandboard (fix #2253)
2017-01-23 09:23:55 +00:00
/* System reset controller */
SRC_MMIO_BASE = 0x20d8000,
hw: support Wandboard Quad (i.MX6) The port uses the Cortex-A9 private timer for the kernel and an EPIT as user timer. It was successfully tested on the Wandboard Quad and the CuBox-i with the signal test. It lacks L2-cache and Trustzone support by now. Thanks to Praveen Srinivas (IIT Madras, India) and Nikolay Golikov (Ksys Labs LLC, Russia). This work is partially based on their contributions. Fix #1467
2015-03-25 18:30:37 +00:00
/* CPU cache */
CACHE_LINE_SIZE_LOG2 = 5,
};
};
base: remove include/spec/* other than ISA This commit moves the headers residing in `repos/base/include/spec/*/drivers` to `repos/base/include/drivers/defs` or repos/base/include/drivers/uart` respectively. The first one contains definitions about board-specific MMIO iand RAM addresses, or IRQ lines. While the latter contains device driver code for UART devices. Those definitions are used by driver implementations in `repos/base-hw`, `repos/os`, and `repos/dde-linux`, which now need to include them more explicitely. This work is a step in the direction of reducing 'SPEC' identifiers overall. Ref #2403
2017-04-28 13:27:26 +00:00
#endif /* _INCLUDE__DRIVERS__DEFS__WAND_QUAD_H_ */
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