Commit Graph

6 Commits

Author SHA1 Message Date
Alexey Brodkin
5f77abf9b0 RISC-V: Remove EXPERIMENTAL tag
It's been a while since RISC-V support was added to CT-NG in 2017.
Since then RISC-V support was integrated in all the key toolchain
components upstream and now are proven to be in a very good state.

Thus it makes no sense to keep this architecture "hidden" in
experimental options, so we promote RISC-V architecture in CT-NG.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2024-09-09 08:58:59 +12:00
Alexey Neyman
858f939436 More sample config updates
*-moxie*: DTC_VERBOSE is a wobbler, it depends on whether dtc is enabled
on the host machine (if dtc is installed, DTC defaults to 'n' and hence
prevents DTC_VERBOSE from appearing at all). Remove the option from
config file so that its value reverts to the default.

xtensa-fsf-elf: mark configuration obsolete so that it can use GDB 8.1
(it uses custom sources and needs to select the version therein)

Signed-off-by: Alexey Neyman <stilor@att.net>
2022-02-11 00:47:51 -08:00
Alexey Neyman
5332f480e4 Update the samples to v3
Signed-off-by: Alexey Neyman <stilor@att.net>
2019-03-09 19:42:34 -08:00
Alexey Neyman
47e16f64e4 Run the samples through update to v2
Signed-off-by: Alexey Neyman <stilor@att.net>
2019-02-09 15:55:37 -08:00
Alexey Neyman
93dd61e257 Run the samples through ct-ng update-samples
- Pin sparc-leon-linux-gnu to GCC6, again.
- Remove "brokenness" explanation from moxie-elf comment (was only
applicable to stage-2 compiler, not final).

Signed-off-by: Alexey Neyman <stilor@att.net>
2019-01-28 22:46:15 -08:00
Paul Walmsley
af8da8b181 riscv64: add rv64gc bare-metal sample
This sample works well for building the open-source first stage
bootloader for the SiFive U540 device (and similar):

https://github.com/sifive/freedom-u540-c000-bootloader

Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
2018-09-24 11:09:39 -07:00