mirror of
https://github.com/corda/corda.git
synced 2025-01-23 21:08:48 +00:00
More emitters and such; probably not compiling.
This commit is contained in:
JET
parent
97bc388f57
commit
fab278f09d
197
src/arm.cpp
197
src/arm.cpp
@ -148,14 +148,44 @@ inline int fadds(int Sd, int Sn, int Sm) { return COOP(AL, (Sd&1)<<2|3, Sn>>1, S
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inline int fsubs(int Sd, int Sn, int Sm) { return COOP(AL, (Sd&1)<<2|3, Sn>>1, Sd>>1, 10, (Sn&1)<<2|(Sm&1)|2, Sm>>1); }
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inline int fdivs(int Sd, int Sn, int Sm) { return COOP(AL, (Sd&1)<<2|8, Sn>>1, Sd>>1, 10, (Sn&1)<<2|(Sm&1), Sm>>1); }
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inline int fmacd(int Dd, int Dn, int Dm) { return COOP(AL, 0, Dn, Dd, 11, 0, Dm); }
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inline int fnmacd(int Dd, int Dn, int Dm) { return COOP(AL, 0, Dn, Dd, 11, 2, Dm); }
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inline int fmscd(int Dd, int Dn, int Dm) { return COOP(AL, 1, Dn, Dd, 11, 0, Dm); }
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inline int fnmscd(int Dd, int Dn, int Dm) { return COOP(AL, 1, Dn, Dd, 11, 2, Dm); }
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inline int fmuld(int Dd, int Dn, int Dm) { return COOP(AL, 2, Dn, Dd, 11, 0, Dm); }
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inline int fnmuld(int Dd, int Dn, int Dm) { return COOP(AL, 2, Dn, Dd, 11, 2, Dm); }
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inline int faddd(int Dd, int Dn, int Dm) { return COOP(AL, 3, Dn, Dd, 11, 0, Dm); }
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inline int fsubd(int Dd, int Dn, int Dm) { return COOP(AL, 3, Dn, Dd, 11, 2, Dm); }
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inline int fdivd(int Dd, int Dn, int Dm) { return COOP(AL, 8, Dn, Dd, 11, 0, Dm); }
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inline int fnmacd(int Dd, int Dn, int Dm) { return COOP(AL, 0, Dn, Dd, 11, 2, Dm); }
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inline int fmscd(int Dd, int Dn, int Dm) { return COOP(AL, 1, Dn, Dd, 11, 0, Dm); }
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inline int fnmscd(int Dd, int Dn, int Dm) { return COOP(AL, 1, Dn, Dd, 11, 2, Dm); }
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inline int fmuld(int Dd, int Dn, int Dm) { return COOP(AL, 2, Dn, Dd, 11, 0, Dm); }
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inline int fnmuld(int Dd, int Dn, int Dm) { return COOP(AL, 2, Dn, Dd, 11, 2, Dm); }
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inline int faddd(int Dd, int Dn, int Dm) { return COOP(AL, 3, Dn, Dd, 11, 0, Dm); }
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inline int fsubd(int Dd, int Dn, int Dm) { return COOP(AL, 3, Dn, Dd, 11, 2, Dm); }
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inline int fdivd(int Dd, int Dn, int Dm) { return COOP(AL, 8, Dn, Dd, 11, 0, Dm); }
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inline int fcpys(int Sd, int Sm) { return COOP(AL, 0xb|Sd&1, 0, Sd, 10, 2|Sm&1, Sm); }
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inline int fabss(int Sd, int Sm) { return COOP(AL, 0xb|Sd&1, 0, Sd, 10, 6|Sm&1, Sm); }
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inline int fnegs(int Sd, int Sm) { return COOP(AL, 0xb|Sd&1, 1, Sd, 10, 2|Sm&1, Sm); }
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inline int fsqrts(int Sd, int Sm) { return COOP(AL, 0xb|Sd&1, 1, Sd, 10, 6|Sm&1, Sm); }
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inline int fcmps(int Sd, int Sm) { return COOP(AL, 0xb|Sd&1, 4, Sd, 10, 2|Sm&1, Sm); }
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inline int fcmpes(int Sd, int Sm) { return COOP(AL, 0xb|Sd&1, 4, Sd, 10, 6|Sm&1, Sm); }
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inline int fcmpzs(int Sd) { return COOP(AL, 0xb|Sd&1, 5, Sd, 10, 2|Sm&1, 0); }
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inline int fcmpezs(int Sd) { return COOP(AL, 0xb|Sd&1, 5, Sd, 10, 6|Sm&1, 0); }
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inline int fcvtds(int Dd, int Sm) { return COOP(AL, 0xb|Sd&1, 7, Dd, 10, 6|Sm&1, Sm); }
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inline int fuitos(int Sd, int Sm) { return COOP(AL, 0xb|Sd&1, 8, Sd, 10, 2|Sm&1, Sm); }
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inline int fsitos(int Sd, int Sm) { return COOP(AL, 0xb|Sd&1, 8, Sd, 10, 6|Sm&1, Sm); }
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inline int ftouis(int Sd, int Sm) { return COOP(AL, 0xb|Sd&1, 0xc, Sd, 10, 2|Sm&1, Sm); }
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inline int ftouizs(int Sd, int Sm) { return COOP(AL, 0xb|Sd&1, 0xc, Sd, 10, 6|Sm&1, Sm); }
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inline int ftosis(int Sd, int Sm) { return COOP(AL, 0xb|Sd&1, 0xd, Sd, 10, 2|Sm&1, Sm); }
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inline int ftosizs(int Sd, int Sm) { return COOP(AL, 0xb|Sd&1, 0xd, Sd, 10, 6|Sm&1, Sm); }
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inline int fcpyd(int Dd, int Dm) { return COOP(AL, 0xb, 0, Dd, 11, 2, Dm); }
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inline int fabsd(int Dd, int Dm) { return COOP(AL, 0xb, 0, Dd, 11, 6, Dm); }
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inline int fnegd(int Dd, int Dm) { return COOP(AL, 0xb, 1, Dd, 11, 2, Dm); }
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inline int fsqrtd(int Dd, int Dm) { return COOP(AL, 0xb, 1, Dd, 11, 6, Dm); }
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inline int fcmpd(int Dd, int Dm) { return COOP(AL, 0xb, 4, Dd, 11, 2, Dm); }
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inline int fcmped(int Dd, int Dm) { return COOP(AL, 0xb, 4, Dd, 11, 6, Dm); }
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inline int fcmpzd(int Dd) { return COOP(AL, 0xb, 5, Dd, 11, 2, 0); }
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inline int fcmpezd(int Dd) { return COOP(AL, 0xb, 5, Dd, 11, 6, 0); }
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inline int fcvtsd(int Sd, int Dm) { return COOP(AL, 0xb, 7, Sd, 11, 6, Dm); }
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inline int fuitod(int Dd, int Dm) { return COOP(AL, 0xb, 8, Dd, 11, 2, Dm); }
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inline int fsitod(int Dd, int Dm) { return COOP(AL, 0xb, 8, Dd, 11, 6, Dm); }
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inline int ftouid(int Dd, int Dm) { return COOP(AL, 0xb, 0xc, Dd, 11, 2, Dm); }
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inline int ftouizd(int Dd, int Dm) { return COOP(AL, 0xb, 0xc, Dd, 11, 6, Dm); }
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inline int ftosid(int Dd, int Dm) { return COOP(AL, 0xb, 0xd, Dd, 11, 2, Dm); }
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inline int ftosizd(int Dd, int Dm) { return COOP(AL, 0xb, 0xd, Dd, 11, 6, Dm); }
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inline int fldms(int Rn, int Sd, int count) { return COXFER(AL, 0, 1, Sd&1, 0, 1, Rn, Sd>>1, 10, count); }
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inline int fldmd(int Rn, int Dd, int count) { return COXFER(AL, 0, 1, 0, 0, 1, Rn, Dd, 11, count<<1); }
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inline int fldmx(int Rn, int Dd, int count) { return COXFER(AL, 0, 1, 0, 0, 1, Rn, Dd, 11, count<<1|1); }
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@ -200,6 +230,10 @@ inline int ble(int offset) { return SETCOND(b(offset), LE); }
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inline int bge(int offset) { return SETCOND(b(offset), GE); }
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inline int blo(int offset) { return SETCOND(b(offset), CC); }
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inline int bhs(int offset) { return SETCOND(b(offset), CS); }
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// HARDWARE FLAGS
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bool vfpSupported() {
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return true;
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}
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}
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const uint64_t MASK_LO32 = 0xffffffff;
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@ -228,6 +262,11 @@ inline int carry16(target_intptr_t v) { return static_cast<int16_t>(v) < 0 ? 1 :
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inline bool isOfWidth(int64_t i, int size) { return static_cast<uint64_t>(i) >> size == 0; }
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inline bool isOfWidth(int i, int size) { return static_cast<unsigned>(i) >> size == 0; }
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const uint64_t GPR32_MASK = 0xffff;
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const uint64_t GPR64_MASK = 0xffff0000ffff;
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const uint64_t FPR32_MASK = 0xffff00000;
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const uint64_t FPR64_MASK = 0xffff0000;
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const unsigned FrameHeaderSize = 1;
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const unsigned StackAlignmentInBytes = 8;
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@ -534,6 +573,7 @@ using namespace isa;
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// shortcut functions
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inline void emit(Context* con, int code) { con->code.append4(code); }
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inline int newTemp(Context* con) { return con->client->acquireTemporary(); }
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inline int newTemp(Context* con, unsigned mask) { return con->client->acquireTemporary(mask); }
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inline void freeTemp(Context* con, int r) { con->client->releaseTemporary(r); }
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inline int64_t getValue(Assembler::Constant* c) { return c->value->value(); }
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@ -1002,17 +1042,87 @@ void multiplyR(Context* con, unsigned size, Assembler::Register* a, Assembler::R
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}
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}
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void floatAbsoluteRR(Context* con, unsigned size, Assembler::Register* a, unsigned UNUSED, Assembler::Register* b) {
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if (size == 8) {
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emit(con, fabsd(b->low, a->low));
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} else {
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emit(con, fabss(b->low, a->low));
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}
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}
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void floatNegateRR(Context* con, unsigned size, Assembler::Register* a, unsigned UNUSED, Assembler::Register* b) {
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if (size == 8) {
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emit(con, fnegd(b->low, a->low));
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} else {
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emit(con, fnegs(b->low, a->low));
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}
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}
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void float2FloatRR(Context* con, unsigned size, Assembler::Register* a, unsigned UNUSED, Assembler::Register* b) {
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if (size == 8) {
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emit(con, fcvtsd(b->low, a->low));
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} else {
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emit(con, fcvtds(b->low, a->low));
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}
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}
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void float2IntRR(Context* con, unsigned size, Assembler::Register* a, unsigned UNUSED, Assembler::Register* b) {
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int tmp = newTemp(FPR_MASK);
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if (size == 8) { // double to int
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emit(con, ftosid(tmp, a->low));
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} else { // float to int
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emit(con, ftosis(tmp, a->low));
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} // else thunked
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emit(con, fmrs(b->low, tmp));
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freeTemp(con, tmp);
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}
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void int2FloatRR(Context* con, unsigned UNUSED, Assembler::Register* a, unsigned size, Assembler::Register* b) {
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emit(con, fmsr(b->low, a->low));
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if (size == 8) { // int to double
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emit(con, fsitod(b->low, b->low));
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} else { // int to float
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emit(con, fsitos(b->low, b->low));
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} // else thunked
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}
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void floatSqrtRR(Context* con, unsigned size, Assembler::Register* a, unsigned UNUSED, Assembler::Register* b) {
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if (size == 8) {
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emit(con, fsqrtd(b->low, a->low));
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} else {
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emit(con, fsqrts(b->low, a->low));
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}
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}
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void floatAddR(Context* con, unsigned size, Assembler::Register* a, Assembler::Register* b, Assembler::Register* t) {
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if (size == 8) {
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emit(con, faddd(t->low, a->low, b->low));
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} else {
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emit(con, fadds(t->low, a->low, b->low));
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}
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}
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void floatSubtractR(Context* con, unsigned size, Assembler::Register* a, Assembler::Register* b, Assembler::Register* t) {
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if (size == 8) {
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emit(con, fsubd(t->low, a->low, b->low));
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} else {
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emit(con, fsubs(t->low, a->low, b->low));
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}
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}
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void floatMultiplyR(Context* con, unsigned size, Assembler::Register* a, Assembler::Register* b, Assembler::Register* t) {
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if (size == 8) {
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emit(con, fmdrr(0, a->low, a->high));
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emit(con, fmdrr(1, b->low, b->high));
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emit(con, fmuld(0, 0, 1));
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emit(con, fmrrd(t->low, t->high, 0));
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emit(con, fmuld(t->low, a->low, b->low));
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} else {
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emit(con, fmsr(0, a->low));
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emit(con, fmsr(1, b->low));
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emit(con, fmuls(0, 0, 1));
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emit(con, fmrs(t->low, 0));
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emit(con, fmuls(t->low, a->low, b->low));
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}
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}
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void floatDivideR(Context* con, unsigned size, Assembler::Register* a, Assembler::Register* b, Assembler::Register* t) {
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if (size == 8) {
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emit(con, fdivd(t->low, a->low, b->low));
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} else {
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emit(con, fdivs(t->low, a->low, b->low));
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}
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}
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@ -1815,13 +1925,23 @@ populateTables(ArchitectureContext* c)
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bo[index(c, Negate, R, R)] = CAST2(negateRR);
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bo[index(c, FloatAbsolute, R, R)] = CAST2(floatAbsoluteRR);
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bo[index(c, FloatNegate, R, R)] = CAST2(floatNegateRR);
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bo[index(c, Float2Float, R, R)] = CAST2(float2FloatRR);
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bo[index(c, Float2Int, R, R)] = CAST2(float2IntRR);
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bo[index(c, Int2Float, R, R)] = CAST2(int2FloatRR);
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bo[index(c, FloatSquareRoot, R)] = CAST2(floatSqrtRR);
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to[index(c, Add, R)] = CAST3(addR);
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to[index(c, Subtract, R)] = CAST3(subR);
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to[index(c, Multiply, R)] = CAST3(multiplyR);
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to[index(c, FloatAdd, R)] = CAST3(floatAddR);
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to[index(c, FloatSubtract, R)] = CAST3(floatSubtractR);
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to[index(c, FloatMultiply, R)] = CAST3(floatMultiplyR);
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to[index(c, FloatDivide, R)] = CAST3(floatDivideR);
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to[index(c, ShiftLeft, R)] = CAST3(shiftLeftR);
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to[index(c, ShiftLeft, C)] = CAST3(shiftLeftC);
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@ -1852,15 +1972,15 @@ class MyArchitecture: public Assembler::Architecture {
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}
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virtual unsigned floatRegisterSize() {
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return 0;
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return vfpSupported() ? 16 : 0;
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}
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virtual uint32_t generalRegisterMask() {
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return 0xFFFF;
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return GPR_MASK;
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}
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virtual uint32_t floatRegisterMask() {
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return 0;
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return vfpSupported() ? FPR_MASK : 0;
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}
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virtual int scratch() {
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@ -2062,30 +2182,40 @@ class MyArchitecture: public Assembler::Architecture {
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virtual void planSource
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(BinaryOperation op,
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unsigned, uint8_t* aTypeMask, uint64_t* aRegisterMask,
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unsigned, bool* thunk)
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unsigned aSize, uint8_t* aTypeMask, uint64_t* aRegisterMask,
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unsigned bSize, bool* thunk)
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{
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*aTypeMask = ~0;
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*aRegisterMask = ~static_cast<uint64_t>(0);
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*thunk = false;
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*aTypeMask = (1 << RegisterOperand);
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switch (op) {
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case Negate:
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*aTypeMask = (1 << RegisterOperand);
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break;
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case Absolute:
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case FloatAbsolute:
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case FloatSquareRoot:
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case FloatNegate:
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case Float2Float:
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if (vfpSupported()) {
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} else {
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*thunk = true;
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}
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break;
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case Float2Int:
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if (vfpSupported() && bSize == 4) {
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} else {
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*thunk = true;
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}
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break;
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case Int2Float:
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*thunk = true;
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if (vfpSupported() && aSize == 4) {
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} else {
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*thunk = true;
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}
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break;
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default:
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*aRegisterMask = ~static_cast<uint64_t>(0);
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*thunk = false;
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break;
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}
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}
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@ -2153,7 +2283,6 @@ class MyArchitecture: public Assembler::Architecture {
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case Or:
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case Xor:
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case Multiply:
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case FloatMultiply:
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*aTypeMask = *bTypeMask = (1 << RegisterOperand);
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break;
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@ -2161,6 +2290,7 @@ class MyArchitecture: public Assembler::Architecture {
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case Remainder:
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case FloatAdd:
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case FloatSubtract:
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case FloatMultiply:
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case FloatDivide:
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case FloatRemainder:
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case JumpIfFloatEqual:
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@ -2173,7 +2303,10 @@ class MyArchitecture: public Assembler::Architecture {
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case JumpIfFloatGreaterOrUnordered:
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case JumpIfFloatLessOrEqualOrUnordered:
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case JumpIfFloatGreaterOrEqualOrUnordered:
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*thunk = true;
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if (vfpSupported()) {
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} else {
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*thunk = true;
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}
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break;
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default:
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