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fix register masks used for planning in arm.cpp
We can't use a floating point register where an integer register is needed, or we may generate an invalid instruction.
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95cf6cf941
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@ -2396,7 +2396,7 @@ class MyArchitecture: public Assembler::Architecture {
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{
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*thunk = false;
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*aTypeMask = ~0;
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*aRegisterMask = ~static_cast<uint64_t>(0);
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*aRegisterMask = GPR_MASK64;
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switch (op) {
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case Negate:
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@ -2453,7 +2453,7 @@ class MyArchitecture: public Assembler::Architecture {
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unsigned , uint8_t* bTypeMask, uint64_t* bRegisterMask)
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{
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*bTypeMask = (1 << RegisterOperand) | (1 << MemoryOperand);
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*bRegisterMask = ~static_cast<uint64_t>(0);
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*bRegisterMask = GPR_MASK64;
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switch (op) {
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case Negate:
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@ -2584,7 +2584,7 @@ class MyArchitecture: public Assembler::Architecture {
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virtual void planDestination
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(TernaryOperation op,
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unsigned, uint8_t, uint64_t,
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unsigned, uint8_t, const uint64_t,
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unsigned, uint8_t, const uint64_t bRegisterMask,
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unsigned, uint8_t* cTypeMask, uint64_t* cRegisterMask)
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{
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if (isBranch(op)) {
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@ -2592,7 +2592,7 @@ class MyArchitecture: public Assembler::Architecture {
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*cRegisterMask = 0;
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} else {
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*cTypeMask = (1 << RegisterOperand);
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*cRegisterMask = ~static_cast<uint64_t>(0);
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*cRegisterMask = bRegisterMask;
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}
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}
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