From 127d56d0feb61aeb2d72ca6556dc823156ba4731 Mon Sep 17 00:00:00 2001
From: Joel Dice <joel.dice@gmail.com>
Date: Mon, 13 Aug 2012 09:19:42 +0000
Subject: [PATCH] fix register masks used for planning in arm.cpp

We can't use a floating point register where an integer register is
needed, or we may generate an invalid instruction.
---
 src/arm.cpp | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/arm.cpp b/src/arm.cpp
index 1ff42c037d..97f9455495 100644
--- a/src/arm.cpp
+++ b/src/arm.cpp
@@ -2396,7 +2396,7 @@ class MyArchitecture: public Assembler::Architecture {
   {
     *thunk = false;
     *aTypeMask = ~0;
-    *aRegisterMask = ~static_cast<uint64_t>(0);
+    *aRegisterMask = GPR_MASK64;
 
     switch (op) {
     case Negate:
@@ -2453,7 +2453,7 @@ class MyArchitecture: public Assembler::Architecture {
    unsigned , uint8_t* bTypeMask, uint64_t* bRegisterMask)
   {
     *bTypeMask = (1 << RegisterOperand) | (1 << MemoryOperand);
-    *bRegisterMask = ~static_cast<uint64_t>(0);
+    *bRegisterMask = GPR_MASK64;
 
     switch (op) {
     case Negate:
@@ -2584,7 +2584,7 @@ class MyArchitecture: public Assembler::Architecture {
   virtual void planDestination
   (TernaryOperation op,
    unsigned, uint8_t, uint64_t,
-   unsigned, uint8_t, const uint64_t,
+   unsigned, uint8_t, const uint64_t bRegisterMask,
    unsigned, uint8_t* cTypeMask, uint64_t* cRegisterMask)
   {
     if (isBranch(op)) {
@@ -2592,7 +2592,7 @@ class MyArchitecture: public Assembler::Architecture {
       *cRegisterMask = 0;
     } else {
       *cTypeMask = (1 << RegisterOperand);
-      *cRegisterMask = ~static_cast<uint64_t>(0);
+      *cRegisterMask = bRegisterMask;
     }
   }