mirror of
https://github.com/ggerganov/whisper.cpp.git
synced 2024-12-22 05:57:48 +00:00
b17ba2815b
* CUDA: faster q2_K, q3_K MMQ + int8 tensor cores * try CI fix * try CI fix * try CI fix * fix data race * rever q2_K precision related changes
105 lines
3.3 KiB
Plaintext
105 lines
3.3 KiB
Plaintext
#include "argsort.cuh"
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template<typename T>
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static inline __device__ void ggml_cuda_swap(T & a, T & b) {
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T tmp = a;
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a = b;
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b = tmp;
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}
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template<ggml_sort_order order>
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static __global__ void k_argsort_f32_i32(const float * x, int * dst, const int ncols, int ncols_pad) {
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// bitonic sort
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int col = threadIdx.x;
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int row = blockIdx.y;
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if (col >= ncols_pad) {
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return;
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}
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const float * x_row = x + row * ncols;
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extern __shared__ int dst_row[];
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// initialize indices
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dst_row[col] = col;
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__syncthreads();
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for (int k = 2; k <= ncols_pad; k *= 2) {
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for (int j = k / 2; j > 0; j /= 2) {
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int ixj = col ^ j;
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if (ixj > col) {
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if ((col & k) == 0) {
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if (dst_row[col] >= ncols ||
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(dst_row[ixj] < ncols && (order == GGML_SORT_ORDER_ASC ?
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x_row[dst_row[col]] > x_row[dst_row[ixj]] :
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x_row[dst_row[col]] < x_row[dst_row[ixj]]))
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) {
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ggml_cuda_swap(dst_row[col], dst_row[ixj]);
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}
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} else {
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if (dst_row[ixj] >= ncols ||
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(dst_row[col] < ncols && (order == GGML_SORT_ORDER_ASC ?
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x_row[dst_row[col]] < x_row[dst_row[ixj]] :
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x_row[dst_row[col]] > x_row[dst_row[ixj]]))
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) {
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ggml_cuda_swap(dst_row[col], dst_row[ixj]);
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}
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}
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}
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__syncthreads();
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}
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}
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// copy the result to dst without the padding
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if (col < ncols) {
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dst[row * ncols + col] = dst_row[col];
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}
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}
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static int next_power_of_2(int x) {
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int n = 1;
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while (n < x) {
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n *= 2;
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}
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return n;
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}
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static void argsort_f32_i32_cuda(const float * x, int * dst, const int ncols, const int nrows, ggml_sort_order order, cudaStream_t stream) {
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// bitonic sort requires ncols to be power of 2
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const int ncols_pad = next_power_of_2(ncols);
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const dim3 block_dims(ncols_pad, 1, 1);
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const dim3 block_nums(1, nrows, 1);
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const size_t shared_mem = ncols_pad * sizeof(int);
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// FIXME: this limit could be raised by ~2-4x on Ampere or newer
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GGML_ASSERT(shared_mem <= ggml_cuda_info().devices[ggml_cuda_get_device()].smpb);
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if (order == GGML_SORT_ORDER_ASC) {
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k_argsort_f32_i32<GGML_SORT_ORDER_ASC><<<block_nums, block_dims, shared_mem, stream>>>(x, dst, ncols, ncols_pad);
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} else if (order == GGML_SORT_ORDER_DESC) {
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k_argsort_f32_i32<GGML_SORT_ORDER_DESC><<<block_nums, block_dims, shared_mem, stream>>>(x, dst, ncols, ncols_pad);
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} else {
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GGML_ASSERT(false);
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}
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}
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void ggml_cuda_op_argsort(ggml_backend_cuda_context & ctx, ggml_tensor * dst) {
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const ggml_tensor * src0 = dst->src[0];
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const float * src0_d = (const float *)src0->data;
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float * dst_d = (float *)dst->data;
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cudaStream_t stream = ctx.stream();
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GGML_ASSERT(src0->type == GGML_TYPE_F32);
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GGML_ASSERT( dst->type == GGML_TYPE_I32);
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GGML_ASSERT(ggml_is_contiguous(src0));
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const int64_t ncols = src0->ne[0];
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const int64_t nrows = ggml_nrows(src0);
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enum ggml_sort_order order = (enum ggml_sort_order) dst->op_params[0];
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argsort_f32_i32_cuda(src0_d, (int *)dst_d, ncols, nrows, order, stream);
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}
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