mirror of
https://github.com/ggerganov/whisper.cpp.git
synced 2024-12-23 22:42:22 +00:00
e08c62149b
* CUDA: refactor mmq, dmmv, mmvq * fix out-of-bounds write * struct for qk, qr, qi * fix cmake build * mmq_type_traits
420 lines
18 KiB
Plaintext
420 lines
18 KiB
Plaintext
#include "mmvq.cuh"
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#include "vecdotq.cuh"
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typedef float (*vec_dot_q_cuda_t)(const void * __restrict__ vbq, const block_q8_1 * __restrict__ bq8_1, const int & kbx, const int & iqs);
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static constexpr __device__ vec_dot_q_cuda_t get_vec_dot_q_cuda(ggml_type type) {
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return type == GGML_TYPE_Q4_0 ? vec_dot_q4_0_q8_1 :
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type == GGML_TYPE_Q4_1 ? vec_dot_q4_1_q8_1 :
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type == GGML_TYPE_Q5_0 ? vec_dot_q5_0_q8_1 :
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type == GGML_TYPE_Q5_1 ? vec_dot_q5_1_q8_1 :
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type == GGML_TYPE_Q8_0 ? vec_dot_q8_0_q8_1 :
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type == GGML_TYPE_Q2_K ? vec_dot_q2_K_q8_1 :
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type == GGML_TYPE_Q3_K ? vec_dot_q3_K_q8_1 :
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type == GGML_TYPE_Q4_K ? vec_dot_q4_K_q8_1 :
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type == GGML_TYPE_Q5_K ? vec_dot_q5_K_q8_1 :
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type == GGML_TYPE_Q6_K ? vec_dot_q6_K_q8_1 :
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type == GGML_TYPE_IQ2_XXS ? vec_dot_iq2_xxs_q8_1 :
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type == GGML_TYPE_IQ2_XS ? vec_dot_iq2_xs_q8_1 :
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type == GGML_TYPE_IQ2_S ? vec_dot_iq2_s_q8_1 :
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type == GGML_TYPE_IQ3_XXS ? vec_dot_iq3_xxs_q8_1 :
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type == GGML_TYPE_IQ1_S ? vec_dot_iq1_s_q8_1 :
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type == GGML_TYPE_IQ1_M ? vec_dot_iq1_m_q8_1 :
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type == GGML_TYPE_IQ4_NL ? vec_dot_iq4_nl_q8_1 :
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type == GGML_TYPE_IQ4_XS ? vec_dot_iq4_xs_q8_1 :
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type == GGML_TYPE_IQ3_S ? vec_dot_iq3_s_q8_1 :
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nullptr;
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}
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static constexpr __device__ int get_vdr_mmvq(ggml_type type) {
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return type == GGML_TYPE_Q4_0 ? VDR_Q4_0_Q8_1_MMVQ :
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type == GGML_TYPE_Q4_1 ? VDR_Q4_1_Q8_1_MMVQ :
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type == GGML_TYPE_Q5_0 ? VDR_Q5_0_Q8_1_MMVQ :
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type == GGML_TYPE_Q5_1 ? VDR_Q5_1_Q8_1_MMVQ :
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type == GGML_TYPE_Q8_0 ? VDR_Q8_0_Q8_1_MMVQ :
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type == GGML_TYPE_Q2_K ? VDR_Q2_K_Q8_1_MMVQ :
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type == GGML_TYPE_Q3_K ? VDR_Q3_K_Q8_1_MMVQ :
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type == GGML_TYPE_Q4_K ? VDR_Q4_K_Q8_1_MMVQ :
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type == GGML_TYPE_Q5_K ? VDR_Q5_K_Q8_1_MMVQ :
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type == GGML_TYPE_Q6_K ? VDR_Q6_K_Q8_1_MMVQ :
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type == GGML_TYPE_IQ4_NL ? VDR_Q4_K_Q8_1_MMVQ :
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1;
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}
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template <ggml_type type, int ncols_y>
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#if !(defined(GGML_USE_HIPBLAS) && defined(__HIP_PLATFORM_AMD__))
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// tell the compiler to use as many registers as it wants, see nwarps definition below
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__launch_bounds__((ncols_y <= 4 ? 4 : 2)*WARP_SIZE, 1)
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#endif // !(defined(GGML_USE_HIPBLAS) && defined(__HIP_PLATFORM_AMD__))
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static __global__ void mul_mat_vec_q(
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const void * __restrict__ vx, const void * __restrict__ vy, float * __restrict__ dst,
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const int ncols_x, const int nrows_x, const int nrows_y, const int nrows_dst) {
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constexpr int qk = ggml_cuda_type_traits<type>::qk;
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constexpr int qi = ggml_cuda_type_traits<type>::qi;
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constexpr int vdr = get_vdr_mmvq(type);
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constexpr vec_dot_q_cuda_t vec_dot_q_cuda = get_vec_dot_q_cuda(type);
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#if defined(GGML_USE_HIPBLAS) && defined(__HIP_PLATFORM_AMD__) && (defined(RDNA2) || defined(RDNA3))
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constexpr int nwarps = 1;
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constexpr int rows_per_cuda_block = 1;
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#else
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constexpr int nwarps = ncols_y <= 4 ? 4 : 2;
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constexpr int rows_per_cuda_block = ncols_y == 1 ? 1 : 2;
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#endif // defined(GGML_USE_HIPBLAS) && defined(__HIP_PLATFORM_AMD__) && !defined(RDNA2) && !defined(RDNA3)
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const int tid = WARP_SIZE*threadIdx.y + threadIdx.x;
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const int row0 = rows_per_cuda_block*blockIdx.x;
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const int blocks_per_row_x = ncols_x / qk;
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const int blocks_per_col_y = nrows_y / QK8_1;
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constexpr int blocks_per_iter = vdr * nwarps*WARP_SIZE / qi;
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// partial sum for each thread
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float tmp[ncols_y][rows_per_cuda_block] = {0.0f};
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const block_q8_1 * y = (const block_q8_1 *) vy;
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for (int kbx = tid / (qi/vdr); kbx < blocks_per_row_x; kbx += blocks_per_iter) {
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const int kby = kbx * (qk/QK8_1); // y block index that aligns with kbx
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// x block quant index when casting the quants to int
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const int kqs = vdr * (tid % (qi/vdr));
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#pragma unroll
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for (int j = 0; j < ncols_y; ++j) {
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#pragma unroll
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for (int i = 0; i < rows_per_cuda_block; ++i) {
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tmp[j][i] += vec_dot_q_cuda(vx, &y[j*blocks_per_col_y + kby], (row0 + i)*blocks_per_row_x + kbx, kqs);
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}
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}
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}
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__shared__ float tmp_shared[nwarps-1 > 0 ? nwarps-1 : 1][ncols_y][rows_per_cuda_block][WARP_SIZE];
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if (threadIdx.y > 0) {
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#pragma unroll
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for (int j = 0; j < ncols_y; ++j) {
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#pragma unroll
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for (int i = 0; i < rows_per_cuda_block; ++i) {
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tmp_shared[threadIdx.y-1][j][i][threadIdx.x] = tmp[j][i];
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}
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}
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}
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__syncthreads();
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if (threadIdx.y > 0) {
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return;
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}
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// sum up partial sums and write back result
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#pragma unroll
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for (int j = 0; j < ncols_y; ++j) {
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#pragma unroll
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for (int i = 0; i < rows_per_cuda_block; ++i) {
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#pragma unroll
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for (int l = 0; l < nwarps-1; ++l) {
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tmp[j][i] += tmp_shared[l][j][i][threadIdx.x];
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}
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tmp[j][i] = warp_reduce_sum(tmp[j][i]);
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}
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if (threadIdx.x < rows_per_cuda_block && (rows_per_cuda_block == 1 || row0 + threadIdx.x < nrows_dst)) {
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dst[j*nrows_dst + row0 + threadIdx.x] = tmp[j][threadIdx.x];
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}
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}
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}
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template <ggml_type type>
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static void mul_mat_vec_q_cuda(
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const void * vx, const void * vy, float * dst,
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const int ncols_x, const int nrows_x, const int nrows_y, const int ncols_y, const int nrows_dst, cudaStream_t stream) {
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GGML_ASSERT(ncols_x % ggml_blck_size(type) == 0);
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GGML_ASSERT(ncols_y <= MMVQ_MAX_BATCH_SIZE);
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int id = ggml_cuda_get_device();
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int64_t nwarps = 1;
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int64_t rows_per_cuda_block = 1;
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if (ggml_cuda_info().devices[id].cc < CC_RDNA2) { // NVIDIA and AMD older than RDNA2
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switch(ncols_y) {
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case 1:
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nwarps = 4;
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rows_per_cuda_block = 1;
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break;
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case 2:
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case 3:
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case 4:
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nwarps = 4;
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rows_per_cuda_block = 2;
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break;
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case 5:
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case 6:
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case 7:
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case 8:
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nwarps = 2;
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rows_per_cuda_block = 2;
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break;
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default:
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GGML_ASSERT(false);
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break;
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}
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}
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const int64_t nblocks = (nrows_x + rows_per_cuda_block - 1) / rows_per_cuda_block;
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const dim3 block_nums(nblocks, 1, 1);
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const dim3 block_dims(WARP_SIZE, nwarps, 1);
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switch (ncols_y) {
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case 1:
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mul_mat_vec_q<type, 1><<<block_nums, block_dims, 0, stream>>>(vx, vy, dst, ncols_x, nrows_x, nrows_y, nrows_dst);
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break;
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case 2:
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mul_mat_vec_q<type, 2><<<block_nums, block_dims, 0, stream>>>(vx, vy, dst, ncols_x, nrows_x, nrows_y, nrows_dst);
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break;
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case 3:
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mul_mat_vec_q<type, 3><<<block_nums, block_dims, 0, stream>>>(vx, vy, dst, ncols_x, nrows_x, nrows_y, nrows_dst);
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break;
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case 4:
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mul_mat_vec_q<type, 4><<<block_nums, block_dims, 0, stream>>>(vx, vy, dst, ncols_x, nrows_x, nrows_y, nrows_dst);
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break;
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case 5:
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mul_mat_vec_q<type, 5><<<block_nums, block_dims, 0, stream>>>(vx, vy, dst, ncols_x, nrows_x, nrows_y, nrows_dst);
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break;
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case 6:
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mul_mat_vec_q<type, 6><<<block_nums, block_dims, 0, stream>>>(vx, vy, dst, ncols_x, nrows_x, nrows_y, nrows_dst);
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break;
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case 7:
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mul_mat_vec_q<type, 7><<<block_nums, block_dims, 0, stream>>>(vx, vy, dst, ncols_x, nrows_x, nrows_y, nrows_dst);
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break;
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case 8:
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mul_mat_vec_q<type, 8><<<block_nums, block_dims, 0, stream>>>(vx, vy, dst, ncols_x, nrows_x, nrows_y, nrows_dst);
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break;
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default:
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GGML_ASSERT(false);
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break;
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}
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}
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static void mul_mat_vec_q4_0_q8_1_cuda(
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const void * vx, const void * vy, float * dst,
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const int ncols_x, const int nrows_x, const int nrows_y, const int ncols_y, const int nrows_dst, cudaStream_t stream) {
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mul_mat_vec_q_cuda<GGML_TYPE_Q4_0>(vx, vy, dst, ncols_x, nrows_x, nrows_y, ncols_y, nrows_dst, stream);
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}
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static void mul_mat_vec_q4_1_q8_1_cuda(
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const void * vx, const void * vy, float * dst,
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const int ncols_x, const int nrows_x, const int nrows_y, const int ncols_y, const int nrows_dst, cudaStream_t stream) {
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mul_mat_vec_q_cuda<GGML_TYPE_Q4_1>(vx, vy, dst, ncols_x, nrows_x, nrows_y, ncols_y, nrows_dst, stream);
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}
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static void mul_mat_vec_q5_0_q8_1_cuda(
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const void * vx, const void * vy, float * dst,
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const int ncols_x, const int nrows_x, const int nrows_y, const int ncols_y, const int nrows_dst, cudaStream_t stream) {
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mul_mat_vec_q_cuda<GGML_TYPE_Q5_0>(vx, vy, dst, ncols_x, nrows_x, nrows_y, ncols_y, nrows_dst, stream);
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}
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static void mul_mat_vec_q5_1_q8_1_cuda(
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const void * vx, const void * vy, float * dst,
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const int ncols_x, const int nrows_x, const int nrows_y, const int ncols_y, const int nrows_dst, cudaStream_t stream) {
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mul_mat_vec_q_cuda<GGML_TYPE_Q5_1>(vx, vy, dst, ncols_x, nrows_x, nrows_y, ncols_y, nrows_dst, stream);
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}
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static void mul_mat_vec_q8_0_q8_1_cuda(
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const void * vx, const void * vy, float * dst,
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const int ncols_x, const int nrows_x, const int nrows_y, const int ncols_y, const int nrows_dst, cudaStream_t stream) {
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mul_mat_vec_q_cuda<GGML_TYPE_Q8_0>(vx, vy, dst, ncols_x, nrows_x, nrows_y, ncols_y, nrows_dst, stream);
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}
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static void mul_mat_vec_q2_K_q8_1_cuda(
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const void * vx, const void * vy, float * dst,
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const int ncols_x, const int nrows_x, const int nrows_y, const int ncols_y, const int nrows_dst, cudaStream_t stream) {
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mul_mat_vec_q_cuda<GGML_TYPE_Q2_K>(vx, vy, dst, ncols_x, nrows_x, nrows_y, ncols_y, nrows_dst, stream);
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}
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static void mul_mat_vec_q3_K_q8_1_cuda(
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const void * vx, const void * vy, float * dst,
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const int ncols_x, const int nrows_x, const int nrows_y, const int ncols_y, const int nrows_dst, cudaStream_t stream) {
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mul_mat_vec_q_cuda<GGML_TYPE_Q3_K>(vx, vy, dst, ncols_x, nrows_x, nrows_y, ncols_y, nrows_dst, stream);
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}
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static void mul_mat_vec_q4_K_q8_1_cuda(
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const void * vx, const void * vy, float * dst,
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const int ncols_x, const int nrows_x, const int nrows_y, const int ncols_y, const int nrows_dst, cudaStream_t stream) {
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mul_mat_vec_q_cuda<GGML_TYPE_Q4_K>(vx, vy, dst, ncols_x, nrows_x, nrows_y, ncols_y, nrows_dst, stream);
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}
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static void mul_mat_vec_q5_K_q8_1_cuda(
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const void * vx, const void * vy, float * dst,
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const int ncols_x, const int nrows_x, const int nrows_y, const int ncols_y, const int nrows_dst, cudaStream_t stream) {
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mul_mat_vec_q_cuda<GGML_TYPE_Q5_K>(vx, vy, dst, ncols_x, nrows_x, nrows_y, ncols_y, nrows_dst, stream);
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}
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static void mul_mat_vec_q6_K_q8_1_cuda(
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const void * vx, const void * vy, float * dst,
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const int ncols_x, const int nrows_x, const int nrows_y, const int ncols_y, const int nrows_dst, cudaStream_t stream) {
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mul_mat_vec_q_cuda<GGML_TYPE_Q6_K>(vx, vy, dst, ncols_x, nrows_x, nrows_y, ncols_y, nrows_dst, stream);
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}
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static void mul_mat_vec_iq2_xxs_q8_1_cuda(
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const void * vx, const void * vy, float * dst,
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const int ncols_x, const int nrows_x, const int nrows_y, const int ncols_y, const int nrows_dst, cudaStream_t stream) {
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mul_mat_vec_q_cuda<GGML_TYPE_IQ2_XXS>(vx, vy, dst, ncols_x, nrows_x, nrows_y, ncols_y, nrows_dst, stream);
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}
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static void mul_mat_vec_iq2_xs_q8_1_cuda(
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const void * vx, const void * vy, float * dst,
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const int ncols_x, const int nrows_x, const int nrows_y, const int ncols_y, const int nrows_dst, cudaStream_t stream) {
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mul_mat_vec_q_cuda<GGML_TYPE_IQ2_XS>(vx, vy, dst, ncols_x, nrows_x, nrows_y, ncols_y, nrows_dst, stream);
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}
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static void mul_mat_vec_iq2_s_q8_1_cuda(
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const void * vx, const void * vy, float * dst,
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const int ncols_x, const int nrows_x, const int nrows_y, const int ncols_y, const int nrows_dst, cudaStream_t stream) {
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mul_mat_vec_q_cuda<GGML_TYPE_IQ2_S>(vx, vy, dst, ncols_x, nrows_x, nrows_y, ncols_y, nrows_dst, stream);
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}
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static void mul_mat_vec_iq3_xxs_q8_1_cuda(
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const void * vx, const void * vy, float * dst,
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const int ncols_x, const int nrows_x, const int nrows_y, const int ncols_y, const int nrows_dst, cudaStream_t stream) {
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mul_mat_vec_q_cuda<GGML_TYPE_IQ3_XXS>(vx, vy, dst, ncols_x, nrows_x, nrows_y, ncols_y, nrows_dst, stream);
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}
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static void mul_mat_vec_iq1_s_q8_1_cuda(
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const void * vx, const void * vy, float * dst,
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const int ncols_x, const int nrows_x, const int nrows_y, const int ncols_y, const int nrows_dst, cudaStream_t stream) {
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mul_mat_vec_q_cuda<GGML_TYPE_IQ1_S>(vx, vy, dst, ncols_x, nrows_x, nrows_y, ncols_y, nrows_dst, stream);
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}
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static void mul_mat_vec_iq1_m_q8_1_cuda(
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const void * vx, const void * vy, float * dst,
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const int ncols_x, const int nrows_x, const int nrows_y, const int ncols_y, const int nrows_dst, cudaStream_t stream) {
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mul_mat_vec_q_cuda<GGML_TYPE_IQ1_M>(vx, vy, dst, ncols_x, nrows_x, nrows_y, ncols_y, nrows_dst, stream);
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}
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static void mul_mat_vec_iq4_nl_q8_1_cuda(
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const void * vx, const void * vy, float * dst,
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const int ncols_x, const int nrows_x, const int nrows_y, const int ncols_y, const int nrows_dst, cudaStream_t stream) {
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mul_mat_vec_q_cuda<GGML_TYPE_IQ4_NL>(vx, vy, dst, ncols_x, nrows_x, nrows_y, ncols_y, nrows_dst, stream);
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}
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static void mul_mat_vec_iq4_xs_q8_1_cuda(
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const void * vx, const void * vy, float * dst,
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const int ncols_x, const int nrows_x, const int nrows_y, const int ncols_y, const int nrows_dst, cudaStream_t stream) {
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mul_mat_vec_q_cuda<GGML_TYPE_IQ4_XS>(vx, vy, dst, ncols_x, nrows_x, nrows_y, ncols_y, nrows_dst, stream);
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}
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static void mul_mat_vec_iq3_s_q8_1_cuda(
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const void * vx, const void * vy, float * dst,
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const int ncols_x, const int nrows_x, const int nrows_y, const int ncols_y, const int nrows_dst, cudaStream_t stream) {
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mul_mat_vec_q_cuda<GGML_TYPE_IQ3_S>(vx, vy, dst, ncols_x, nrows_x, nrows_y, ncols_y, nrows_dst, stream);
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}
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void ggml_cuda_op_mul_mat_vec_q(
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ggml_backend_cuda_context & ctx,
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const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst, const char * src0_dd_i, const float * src1_ddf_i,
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const char * src1_ddq_i, float * dst_dd_i, const int64_t row_low, const int64_t row_high, const int64_t src1_ncols,
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const int64_t src1_padded_row_size, cudaStream_t stream) {
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const int64_t ne00 = src0->ne[0];
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const int64_t row_diff = row_high - row_low;
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const int64_t ne10 = src1->ne[0];
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GGML_ASSERT(ne10 % QK8_1 == 0);
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const int64_t ne0 = dst->ne[0];
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int id = ggml_cuda_get_device();
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// the main device has a larger memory buffer to hold the results from all GPUs
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// nrows_dst == nrows of the matrix that the kernel writes into
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const int64_t nrows_dst = id == ctx.device ? ne0 : row_diff;
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switch (src0->type) {
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case GGML_TYPE_Q4_0:
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mul_mat_vec_q4_0_q8_1_cuda(src0_dd_i, src1_ddq_i, dst_dd_i, ne00, row_diff, src1_padded_row_size, src1_ncols, nrows_dst, stream);
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break;
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case GGML_TYPE_Q4_1:
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mul_mat_vec_q4_1_q8_1_cuda(src0_dd_i, src1_ddq_i, dst_dd_i, ne00, row_diff, src1_padded_row_size, src1_ncols, nrows_dst, stream);
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break;
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case GGML_TYPE_Q5_0:
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mul_mat_vec_q5_0_q8_1_cuda(src0_dd_i, src1_ddq_i, dst_dd_i, ne00, row_diff, src1_padded_row_size, src1_ncols, nrows_dst, stream);
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break;
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case GGML_TYPE_Q5_1:
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mul_mat_vec_q5_1_q8_1_cuda(src0_dd_i, src1_ddq_i, dst_dd_i, ne00, row_diff, src1_padded_row_size, src1_ncols, nrows_dst, stream);
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break;
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case GGML_TYPE_Q8_0:
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mul_mat_vec_q8_0_q8_1_cuda(src0_dd_i, src1_ddq_i, dst_dd_i, ne00, row_diff, src1_padded_row_size, src1_ncols, nrows_dst, stream);
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break;
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case GGML_TYPE_Q2_K:
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mul_mat_vec_q2_K_q8_1_cuda(src0_dd_i, src1_ddq_i, dst_dd_i, ne00, row_diff, src1_padded_row_size, src1_ncols, nrows_dst, stream);
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break;
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case GGML_TYPE_Q3_K:
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mul_mat_vec_q3_K_q8_1_cuda(src0_dd_i, src1_ddq_i, dst_dd_i, ne00, row_diff, src1_padded_row_size, src1_ncols, nrows_dst, stream);
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break;
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case GGML_TYPE_Q4_K:
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mul_mat_vec_q4_K_q8_1_cuda(src0_dd_i, src1_ddq_i, dst_dd_i, ne00, row_diff, src1_padded_row_size, src1_ncols, nrows_dst, stream);
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break;
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case GGML_TYPE_Q5_K:
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mul_mat_vec_q5_K_q8_1_cuda(src0_dd_i, src1_ddq_i, dst_dd_i, ne00, row_diff, src1_padded_row_size, src1_ncols, nrows_dst, stream);
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break;
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case GGML_TYPE_Q6_K:
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mul_mat_vec_q6_K_q8_1_cuda(src0_dd_i, src1_ddq_i, dst_dd_i, ne00, row_diff, src1_padded_row_size, src1_ncols, nrows_dst, stream);
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break;
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case GGML_TYPE_IQ2_XXS:
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mul_mat_vec_iq2_xxs_q8_1_cuda(src0_dd_i, src1_ddq_i, dst_dd_i, ne00, row_diff, src1_padded_row_size, src1_ncols, nrows_dst, stream);
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break;
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case GGML_TYPE_IQ2_XS:
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mul_mat_vec_iq2_xs_q8_1_cuda(src0_dd_i, src1_ddq_i, dst_dd_i, ne00, row_diff, src1_padded_row_size, src1_ncols, nrows_dst, stream);
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break;
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case GGML_TYPE_IQ2_S:
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mul_mat_vec_iq2_s_q8_1_cuda(src0_dd_i, src1_ddq_i, dst_dd_i, ne00, row_diff, src1_padded_row_size, src1_ncols, nrows_dst, stream);
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break;
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case GGML_TYPE_IQ3_XXS:
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mul_mat_vec_iq3_xxs_q8_1_cuda(src0_dd_i, src1_ddq_i, dst_dd_i, ne00, row_diff, src1_padded_row_size, src1_ncols, nrows_dst, stream);
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break;
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case GGML_TYPE_IQ1_S:
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mul_mat_vec_iq1_s_q8_1_cuda(src0_dd_i, src1_ddq_i, dst_dd_i, ne00, row_diff, src1_padded_row_size, src1_ncols, nrows_dst, stream);
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break;
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case GGML_TYPE_IQ1_M:
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mul_mat_vec_iq1_m_q8_1_cuda(src0_dd_i, src1_ddq_i, dst_dd_i, ne00, row_diff, src1_padded_row_size, src1_ncols, nrows_dst, stream);
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break;
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case GGML_TYPE_IQ4_NL:
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mul_mat_vec_iq4_nl_q8_1_cuda(src0_dd_i, src1_ddq_i, dst_dd_i, ne00, row_diff, src1_padded_row_size, src1_ncols, nrows_dst, stream);
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break;
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case GGML_TYPE_IQ4_XS:
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mul_mat_vec_iq4_xs_q8_1_cuda(src0_dd_i, src1_ddq_i, dst_dd_i, ne00, row_diff, src1_padded_row_size, src1_ncols, nrows_dst, stream);
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break;
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case GGML_TYPE_IQ3_S:
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mul_mat_vec_iq3_s_q8_1_cuda(src0_dd_i, src1_ddq_i, dst_dd_i, ne00, row_diff, src1_padded_row_size, src1_ncols, nrows_dst, stream);
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break;
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default:
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GGML_ASSERT(false);
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break;
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}
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GGML_UNUSED(src1);
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GGML_UNUSED(dst);
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GGML_UNUSED(src1_ddf_i);
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GGML_UNUSED(src1_ncols);
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GGML_UNUSED(src1_padded_row_size);
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}
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