mirror of
https://github.com/nasa/trick.git
synced 2024-12-29 17:38:54 +00:00
483cacfafd
* Add type, dispersion, min_value, max_value and other relevant internal members of MonteCarloVariable* classes to the output of MonteCarlo_Meta_data_output. Motivation is for users wanting to post-process dispersion parameters used during generation of runs * Protect against invalid memory access when length of values is zero in MonteCarloVariableRandomStringSet::generate_assignment(). Add a new verif sim warning case to cover these new lines * Update new verif data for SIM_mc_generation to support these changes Closes #1574 Co-authored-by: Dan Jordan <daniel.d.jordan@nasa.gov>
468 lines
15 KiB
YAML
468 lines
15 KiB
YAML
# Compile only sims
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SIM_alloc_test:
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path: test/SIM_alloc_test
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SIM_alloc_test:
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path: test/SIM_alloc_test
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SIM_anon_enum:
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path: test/SIM_anon_enum
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SIM_default_member_initializer:
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path: test/SIM_default_member_initializer
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SIM_delete_default_constructor:
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path: test/SIM_delete_default_constructor
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SIM_demo_inputfile:
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path: test/SIM_demo_inputfile
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SIM_exclusion_mechanisms:
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path: test/SIM_exclusion_mechanisms
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SIM_isystem:
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path: test/SIM_isystem
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SIM_measurement_units:
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path: test/SIM_measurement_units
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SIM_parse_s_define:
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path: test/SIM_parse_s_define
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SIM_target_specific_variables:
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path: test/SIM_target_specific_variables
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SIM_test_abstract:
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path: test/SIM_test_abstract
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SIM_test_inherit:
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path: test/SIM_test_inherit
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SIM_test_ip2:
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path: test/SIM_test_ip2
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SIM_threads_simple:
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path: test/SIM_threads_simple
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SIM_trickcomm:
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path: test/SIM_trickcomm
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SIM_satellite:
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path: trick_sims/SIM_satellite
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# Normal case compile and run sims
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SIM_demo_sdefine:
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path: test/SIM_demo_sdefine
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build_args: "-t"
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binary: "T_main_{cpu}_test.exe"
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runs:
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RUN_test/unit_test.py:
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returns: 0
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SIM_exec_set_time_tic_value:
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path: test/SIM_exec_set_time_tic_value
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build_args: "-t"
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binary: "T_main_{cpu}_test.exe"
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runs:
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RUN_test/unit_test.py:
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returns: 0
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SIM_python_namespace:
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path: test/SIM_python_namespace
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build_args: "-t"
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binary: "T_main_{cpu}_test.exe"
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runs:
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RUN_test/unit_test.py:
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returns: 0
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SIM_rti:
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path: test/SIM_rti
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build_args: "-t"
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binary: "T_main_{cpu}_test.exe"
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runs:
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RUN_test/unit_test.py:
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returns: 0
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SIM_test_dp:
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path: test/SIM_test_dp
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build_args: "-t"
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binary: "T_main_{cpu}_test.exe"
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runs:
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RUN_test/unit_test.py:
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returns: 0
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SIM_test_icg_file_skipped:
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path: test/SIM_test_icg_file_skipped
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build_args: "-t"
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binary: "T_main_{cpu}_test.exe"
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runs:
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RUN_test/unit_test.py:
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returns: 0
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SIM_test_io:
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path: test/SIM_test_io
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build_args: "-t"
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binary: "T_main_{cpu}_test.exe"
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runs:
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RUN_test/unit_test.py:
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returns: 0
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SIM_test_ip:
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path: test/SIM_test_ip
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build_args: "-t"
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binary: "T_main_{cpu}_test.exe"
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runs:
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RUN_test/unit_test.py:
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returns: 0
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SIM_test_sched:
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path: test/SIM_test_sched
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build_args: "-t"
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binary: "T_main_{cpu}_test.exe"
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runs:
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RUN_test/unit_test.py:
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returns: 0
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SIM_test_templates:
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path: test/SIM_test_templates
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build_args: "-t"
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binary: "T_main_{cpu}_test.exe"
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runs:
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RUN_test/unit_test.py:
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returns: 0
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SIM_threads:
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path: test/SIM_threads
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build_args: "-t"
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binary: "T_main_{cpu}_test.exe"
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runs:
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RUN_test/unit_test.py:
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returns: 0
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SIM_trickified:
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path: test/SIM_trickified
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build_args: "-t"
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binary: "T_main_{cpu}_test.exe"
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runs:
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RUN_test/unit_test.py:
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returns: 0
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SIM_ball_L1:
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path: trick_sims/Ball/SIM_ball_L1
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build_args: "-t"
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binary: "T_main_{cpu}_test.exe"
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runs:
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RUN_test/unit_test.py:
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returns: 0
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SIM_ball_L2:
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path: trick_sims/Ball/SIM_ball_L2
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build_args: "-t"
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binary: "T_main_{cpu}_test.exe"
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runs:
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RUN_test/unit_test.py:
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returns: 0
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SIM_ball_L3:
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path: trick_sims/Ball/SIM_ball_L3
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build_args: "-t"
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binary: "T_main_{cpu}_test.exe"
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runs:
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RUN_test/unit_test.py:
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returns: 0
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SIM_cannon_aero:
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path: trick_sims/Cannon/SIM_cannon_aero
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build_args: "-t"
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binary: "T_main_{cpu}_test.exe"
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runs:
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RUN_test/unit_test.py:
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returns: 0
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SIM_cannon_analytic:
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path: trick_sims/Cannon/SIM_cannon_analytic
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build_args: "-t"
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binary: "T_main_{cpu}_test.exe"
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runs:
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RUN_test/unit_test.py:
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returns: 0
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SIM_cannon_eulercromer:
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path: trick_sims/Cannon/SIM_cannon_eulercromer
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build_args: "-t"
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binary: "T_main_{cpu}_test.exe"
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runs:
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RUN_test/unit_test.py:
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returns: 0
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SIM_cannon_numeric:
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path: trick_sims/Cannon/SIM_cannon_numeric
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build_args: "-t"
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binary: "T_main_{cpu}_test.exe"
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runs:
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RUN_test/unit_test.py:
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returns: 0
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SIM_cannon_jet:
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path: trick_sims/Cannon/SIM_cannon_jet
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build_args: "-t"
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binary: "T_main_{cpu}_test.exe"
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runs:
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RUN_test/unit_test.py:
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returns: 0
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SIM_Ball++_L1:
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path: trick_sims/SIM_Ball++_L1
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build_args: "-t"
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binary: "T_main_{cpu}_test.exe"
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runs:
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RUN_test/unit_test.py:
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returns: 0
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SIM_sun:
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path: trick_sims/SIM_sun
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build_args: "-t"
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binary: "T_main_{cpu}_test.exe"
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runs:
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RUN_test/unit_test.py:
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returns: 0
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SIM_earlyterm:
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path: test/SIM_earlyterm
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build_args: "-t"
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binary: "T_main_{cpu}_test.exe"
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runs:
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RUN_test/input.py:
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returns: 0
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SIM_job_class_order:
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path: test/SIM_job_class_order
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build_args: "-t"
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binary: "T_main_{cpu}_test.exe"
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runs:
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RUN_test/input.py:
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returns: 0
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# Special cases
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# setup.py dumps a checkpoint
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# unit_test.py loads that checkpoint and verifies the data
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SIM_stls:
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path: test/SIM_stls
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build_args: "-t"
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binary: "T_main_{cpu}_test.exe"
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runs:
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RUN_test/setup.py:
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phase: -1
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returns: 0
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RUN_test/unit_test.py:
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returns: 0
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SIM_test_dr:
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path: test/SIM_test_dr
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build_args: "-t"
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binary: "T_main_{cpu}_test.exe"
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runs:
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RUN_test/unit_test.py:
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returns: 0
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compare:
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- test/SIM_test_dr/RUN_test/log_DR_bitfieldsASCII.csv vs. test/SIM_test_dr/RUN_test/Ref_Logs/log_DR_bitfieldsASCII_Master.csv
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- test/SIM_test_dr/RUN_test/log_DR_typesASCII.csv vs. test/SIM_test_dr/RUN_test/Ref_Logs/log_DR_typesASCII_Master.csv
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- test/SIM_test_dr/RUN_test/log_DR_bitfieldsBINARY.trk vs. test/SIM_test_dr/RUN_test/Ref_Logs/log_DR_bitfieldsBINARY.trk
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# All the dump.py runs dump a checkpoint
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# All the unit_test.py runs load that checkpoint and then compare against expected logs
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SIM_checkpoint_data_recording:
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path: test/SIM_checkpoint_data_recording
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build_args: "-t"
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binary: "T_main_{cpu}_test.exe"
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runs:
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RUN_test[1-5]/dump.py:
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phase: -1
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returns: 0
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RUN_test6/dump.py:
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returns: 0
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RUN_test[7-8]/dump.py:
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phase: -1
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returns: 0
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# Note we could use the [1-5] notation here if RUN_test2 didn't stand out as not matching the pattern -Jordan 1/2023
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RUN_test1/unit_test.py:
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returns: 0
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compare:
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- test/SIM_checkpoint_data_recording/RUN_test1/ref_log_foo.csv vs. test/SIM_checkpoint_data_recording/RUN_test1/log_foo.csv
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RUN_test2/unit_test.py:
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returns: 0
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analyze: './test/SIM_checkpoint_data_recording/RUN_test2/check_log.sh'
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RUN_test3/unit_test.py:
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returns: 0
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compare:
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- test/SIM_checkpoint_data_recording/RUN_test3/ref_log_foo.csv vs. test/SIM_checkpoint_data_recording/RUN_test3/log_foo.csv
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RUN_test4/unit_test.py:
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returns: 0
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compare:
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- test/SIM_checkpoint_data_recording/RUN_test4/ref_log_foo.csv vs. test/SIM_checkpoint_data_recording/RUN_test4/log_foo.csv
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RUN_test5/unit_test.py:
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returns: 0
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compare:
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- test/SIM_checkpoint_data_recording/RUN_test5/ref_log_foo.csv vs. test/SIM_checkpoint_data_recording/RUN_test5/log_foo.csv
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RUN_test6/unit_test.py:
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returns: 0
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compare:
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- test/SIM_checkpoint_data_recording/RUN_test6/ref_log_foo2.csv vs. test/SIM_checkpoint_data_recording/RUN_test6/log_foo2.csv
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RUN_test7/unit_test.py:
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returns: 0
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compare:
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- test/SIM_checkpoint_data_recording/RUN_test7/ref_log_fooChange.csv vs. test/SIM_checkpoint_data_recording/RUN_test7/log_fooChange.csv
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RUN_test8/unit_test.py:
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returns: 0
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compare:
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- test/SIM_checkpoint_data_recording/RUN_test8/ref_log_fooChange2.csv vs. test/SIM_checkpoint_data_recording/RUN_test8/log_fooChange2.csv
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SIM_events:
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path: test/SIM_events
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build_args: "-t"
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binary: "T_main_{cpu}_test.exe"
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runs:
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RUN_test/unit_test.py:
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returns: 0
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RUN_test/unit_test_error1.py:
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returns: 255
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RUN_test/unit_test_error2.py:
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returns: 255
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RUN_test/unit_test_error3.py:
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returns: 255
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SIM_test_output_dir:
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path: test/SIM_test_output_dir
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build_args: "-t"
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binary: "T_main_{cpu}_test.exe"
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runs:
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RUN_test/input.py -OO sim_output --read-only-sim:
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returns: 0
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analyze: 'python3 test/SIM_test_output_dir/ref_files/check_file_endings.py test/SIM_test_output_dir/ref_files/ref_compiletime_S_sie.resource test/SIM_test_output_dir/S_sie.resource'
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analyze: 'python3 test/SIM_test_output_dir/ref_files/check_file_endings.py test/SIM_test_output_dir/ref_files/ref_runtime_S_sie.resource test/SIM_test_output_dir/sim_output/S_sie.resource'
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# The variable server client and SIM_amoeba sometimes fail to connect and need to be retried
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# JMP (9/23/2023): We can't have these in our regular CI test suite if they are going to
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# periodically fail due to environmental variations over which we have no control. Commenting
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# these out.
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# SIM_test_varserv:
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# path: test/SIM_test_varserv
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# build_args: "-t"
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# binary: "T_main_{cpu}_test.exe"
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# runs:
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# RUN_test/unit_test.py:
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# phase: 1
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# returns: 0
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# RUN_test/err1_test.py:
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# phase: 2
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# returns: 10
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# RUN_test/err2_test.py:
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# phase: 3
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# returns: 10
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# SIM_amoeba:
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# path: trick_sims/Cannon/SIM_amoeba
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# build_args: "-t"
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# binary: "T_main_{cpu}_test.exe"
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# labels:
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# - retries_allowed
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# runs:
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# RUN_test/unit_test.py:
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# returns: 0
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#TODO: all compares should be <test data> vs. <baseline data>, need to swap order!
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SIM_mc_generation:
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path: test/SIM_mc_generation
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runs:
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RUN_nominal/input_a.py:
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phase: -1
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compare:
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- test/SIM_mc_generation/MONTE_RUN_nominal/MonteCarlo_Meta_data_output vs. test/SIM_mc_generation/verif_data/MONTE_RUN_nominal/MonteCarlo_Meta_data_output
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- test/SIM_mc_generation/MONTE_RUN_nominal/monte_variables vs. test/SIM_mc_generation/verif_data/MONTE_RUN_nominal/monte_variables
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MONTE_RUN_nominal/RUN_[000-001]/monte_input_a.py:
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compare:
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RUN_random_normal_truncate_abs/input.py:
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phase: -1
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compare:
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MONTE_RUN_random_normal_truncate_abs/RUN_[0-9]/monte_input.py:
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compare:
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RUN_random_normal_truncate_rel/input.py:
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phase: -1
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compare:
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MONTE_RUN_random_normal_truncate_rel/RUN_[0-9]/monte_input.py:
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compare:
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RUN_random_normal_truncate_sd/input.py:
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compare:
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phase: -1
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MONTE_RUN_random_normal_truncate_sd/RUN_[0-9]/monte_input.py:
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compare:
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RUN_random_normal__untruncate/input.py:
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compare:
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phase: -1
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MONTE_RUN_random_normal__untruncate/RUN_[0-9]/monte_input.py:
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compare:
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RUN_random_normal_untruncated/input.py:
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compare:
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phase: -1
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MONTE_RUN_random_normal_untruncated/RUN_[0-9]/monte_input.py:
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compare:
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RUN_random_uniform/input.py:
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compare:
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phase: -1
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MONTE_RUN_random_uniform/RUN_[0-9]/monte_input.py:
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compare:
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RUN_ERROR_file_inconsistent_skip/input.py:
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phase: -1
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MONTE_RUN_ERROR_file_inconsistent_skip/RUN_0/monte_input.py:
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RUN_ERROR_invalid_call/input.py:
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compare:
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- test/SIM_mc_generation/MONTE_RUN_ERROR_invalid_call/RUN_0/monte_input.py vs. test/SIM_mc_generation/verif_data/MONTE_RUN_ERROR_invalid_call/RUN_0/monte_input.py
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phase: -1
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MONTE_RUN_ERROR_invalid_call/RUN_0/monte_input.py:
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RUN_ERROR_invalid_name/input.py:
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compare:
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- test/SIM_mc_generation/MONTE_RUN_ERROR_invalid_name/RUN_0/monte_input.py vs. test/SIM_mc_generation/verif_data/MONTE_RUN_ERROR_invalid_name/RUN_0/monte_input.py
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phase: -1
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MONTE_RUN_ERROR_invalid_name/RUN_0/monte_input.py:
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RUN_ERROR_invalid_sequence/input.py:
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compare:
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- test/SIM_mc_generation/MONTE_RUN_ERROR_invalid_sequence/RUN_0/monte_input.py vs. test/SIM_mc_generation/verif_data/MONTE_RUN_ERROR_invalid_sequence/RUN_0/monte_input.py
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phase: -1
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MONTE_RUN_ERROR_invalid_sequence/RUN_0/monte_input.py:
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RUN_ERROR_invalid_sequencing/input.py:
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compare:
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- test/SIM_mc_generation/MONTE_RUN_ERROR_invalid_sequencing/RUN_0/monte_input.py vs. test/SIM_mc_generation/verif_data/MONTE_RUN_ERROR_invalid_sequencing/RUN_0/monte_input.py
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phase: -1
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MONTE_RUN_ERROR_invalid_sequencing/RUN_0/monte_input.py:
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RUN_ERROR_out_of_domain_error/input.py:
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compare:
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phase: -1
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MONTE_RUN_ERROR_out_of_domain_error/RUN_0/monte_input.py:
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RUN_ERROR_random_value_truncation/input.py:
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phase: -1
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MONTE_RUN_ERROR_random_value_truncation/RUN_[0-1]/monte_input.py:
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compare:
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RUN_generate_meta_data_early/input.py:
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compare:
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- test/SIM_mc_generation/MonteCarlo_Meta_data_output vs. test/SIM_mc_generation/verif_data/MonteCarlo_Meta_data_output
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phase: -1
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RUN_file_sequential/input.py:
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compare:
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- test/SIM_mc_generation/MONTE_RUN_file_sequential/monte_values_all_runs vs. test/SIM_mc_generation/verif_data/MONTE_RUN_file_sequential/monte_values_all_runs
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phase: -1
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MONTE_RUN_file_sequential/RUN_[0-9]/monte_input.py:
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compare:
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# Note that technically monte_input.py is an output of RUN_file_sequential, not these runs. The comparisons
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# are only placed here due to limitations of TrickOps [min-max] range notation. See the comment block in
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# TrickWorkflow.Run.multiply() for details. This workaround is also used in more runs for this sim. -Jordan 1/2023
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- test/SIM_mc_generation/MONTE_RUN_file_sequential/RUN_[0-9]/monte_input.py vs. test/SIM_mc_generation/verif_data/MONTE_RUN_file_sequential/RUN_[0-9]/monte_input.py
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RUN_file_skip/input.py:
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phase: -1
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MONTE_RUN_file_skip/RUN_[0-9]/monte_input.py:
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compare:
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RUN_file_skip2/input.py:
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phase: -1
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MONTE_RUN_file_skip2/RUN_[0-4]/monte_input.py:
|
|
RUN_remove_variable/input_a.py:
|
|
compare:
|
|
- test/SIM_mc_generation/MONTE_RUN_remove_variable/RUN_both_variables/monte_variables vs. test/SIM_mc_generation/verif_data/MONTE_RUN_remove_variable/RUN_both_variables/monte_variables
|
|
RUN_remove_variable/input_b.py:
|
|
compare:
|
|
- test/SIM_mc_generation/MONTE_RUN_remove_variable/RUN_one_variable/monte_variables vs. test/SIM_mc_generation/verif_data/MONTE_RUN_remove_variable/RUN_one_variable/monte_variables
|
|
RUN_WARN_config_error/input.py:
|
|
compare:
|
|
phase: -1
|
|
MONTE_RUN_WARN_config_error/RUN_0/monte_input.py:
|
|
RUN_WARN_invalid_name/input.py:
|
|
compare:
|
|
phase: -1
|
|
MONTE_RUN_WARN_invalid_name/RUN_0/monte_input.py:
|
|
RUN_WARN_overconstrained_config/input.py:
|
|
compare:
|
|
phase: -1
|
|
RUN_WARN_no_string_values/input.py:
|
|
compare:
|
|
phase: -1
|
|
MONTE_RUN_WARN_overconstrained_config/RUN_0/monte_input.py:
|
|
FAIL_config_error/input.py:
|
|
returns: 1
|
|
FAIL_duplicate_variable/input.py:
|
|
returns: 1
|
|
FAIL_illegal_config/input.py:
|
|
returns: 1
|
|
FAIL_invalid_config/input.py:
|
|
returns: 1
|
|
FAIL_invalid_data_file/input.py:
|
|
returns: 1
|
|
FAIL_IO_error/input.py:
|
|
returns: 1
|
|
FAIL_malformed_data_file/input.py:
|
|
returns: 1
|