mirror of
https://github.com/servalproject/serval-dna.git
synced 2024-12-26 16:21:09 +00:00
bf9710fd5a
This only affects build_android, if nacl-gcc-prep is run then build/`uname -s` will be created.
299 lines
5.9 KiB
ArmAsm
299 lines
5.9 KiB
ArmAsm
.text
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.p2align 5
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.globl _crypto_scalarmult_curve25519_athlon_square
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.globl crypto_scalarmult_curve25519_athlon_square
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_crypto_scalarmult_curve25519_athlon_square:
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crypto_scalarmult_curve25519_athlon_square:
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mov %esp,%eax
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and $31,%eax
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add $64,%eax
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sub %eax,%esp
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movl 8(%esp,%eax),%edx
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movl 4(%esp,%eax),%ecx
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fldl 72(%edx)
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fmul %st(0),%st(0)
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fldl 0(%edx)
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fadd %st(0),%st(0)
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fldl 8(%edx)
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fadd %st(0),%st(0)
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fldl 16(%edx)
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fadd %st(0),%st(0)
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fldl 56(%edx)
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fxch %st(4)
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fmull crypto_scalarmult_curve25519_athlon_scale
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fldl 72(%edx)
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fmul %st(4),%st(0)
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fldl 64(%edx)
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fmul %st(4),%st(0)
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faddp %st(0),%st(1)
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fxch %st(4)
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fstl 0(%esp)
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fxch %st(3)
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fstl 8(%esp)
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fxch %st(3)
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fmull 64(%edx)
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faddp %st(0),%st(1)
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fldl 48(%edx)
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fxch %st(5)
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fmul %st(0),%st(3)
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fxch %st(3)
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faddp %st(0),%st(1)
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fxch %st(2)
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fadd %st(0),%st(0)
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fldl 56(%edx)
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fmul %st(2),%st(0)
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faddp %st(0),%st(4)
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fxch %st(1)
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fstl 16(%esp)
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fldl 40(%edx)
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fxch %st(5)
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fmul %st(0),%st(1)
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fxch %st(1)
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faddp %st(0),%st(3)
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fadd %st(0),%st(0)
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fstpl 48(%esp)
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fldl 24(%edx)
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fadd %st(0),%st(0)
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fstl 24(%esp)
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fldl 48(%edx)
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fmul %st(1),%st(0)
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faddp %st(0),%st(4)
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fmul %st(4),%st(0)
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faddp %st(0),%st(2)
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fxch %st(3)
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fadd %st(0),%st(0)
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fstpl 40(%esp)
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fldl 32(%edx)
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fmul %st(0),%st(0)
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faddp %st(0),%st(1)
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fldl crypto_scalarmult_curve25519_athlon_alpha230
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fadd %st(1),%st(0)
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fsubl crypto_scalarmult_curve25519_athlon_alpha230
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fsubr %st(0),%st(1)
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fldl 8(%esp)
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fldl 72(%edx)
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fmul %st(0),%st(1)
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fldl 16(%esp)
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fmul %st(0),%st(1)
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fldl 64(%edx)
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fmul %st(0),%st(1)
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fxch %st(1)
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faddp %st(0),%st(3)
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fldl 24(%esp)
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fmul %st(0),%st(1)
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fxch %st(1)
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faddp %st(0),%st(2)
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fldl 32(%edx)
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fadd %st(0),%st(0)
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fstl 32(%esp)
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fmull 40(%edx)
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faddp %st(0),%st(6)
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fxch %st(3)
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faddp %st(0),%st(5)
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fldl crypto_scalarmult_curve25519_athlon_alpha255
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fadd %st(5),%st(0)
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fsubl crypto_scalarmult_curve25519_athlon_alpha255
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fsubr %st(0),%st(5)
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fldl 56(%edx)
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fmul %st(0),%st(4)
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fxch %st(4)
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faddp %st(0),%st(3)
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fldl 32(%esp)
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fmul %st(0),%st(4)
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fxch %st(4)
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faddp %st(0),%st(2)
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fldl 48(%edx)
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fmul %st(0),%st(4)
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fxch %st(4)
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faddp %st(0),%st(3)
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fxch %st(3)
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fmull 40(%esp)
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faddp %st(0),%st(1)
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fxch %st(3)
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fstpl 64(%ecx)
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fldl 40(%edx)
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fmul %st(0),%st(0)
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faddp %st(0),%st(1)
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fxch %st(2)
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fmull crypto_scalarmult_curve25519_athlon_scale
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fxch %st(3)
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fstpl 72(%ecx)
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faddp %st(0),%st(1)
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fmull crypto_scalarmult_curve25519_athlon_scale
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fldl 24(%esp)
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fmull 72(%edx)
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fldl 0(%edx)
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fmul %st(0),%st(0)
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faddp %st(0),%st(2)
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fldl 32(%esp)
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fmull 64(%edx)
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faddp %st(0),%st(1)
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fldl 0(%esp)
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fmull 8(%edx)
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faddp %st(0),%st(3)
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fldl 40(%esp)
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fmull 56(%edx)
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faddp %st(0),%st(1)
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fldl crypto_scalarmult_curve25519_athlon_alpha26
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fadd %st(2),%st(0)
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fsubl crypto_scalarmult_curve25519_athlon_alpha26
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fsubr %st(0),%st(2)
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faddp %st(0),%st(3)
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fldl crypto_scalarmult_curve25519_athlon_alpha51
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fadd %st(3),%st(0)
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fsubl crypto_scalarmult_curve25519_athlon_alpha51
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fsubr %st(0),%st(3)
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fldl 48(%edx)
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fmul %st(0),%st(0)
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faddp %st(0),%st(2)
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fxch %st(1)
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fmull crypto_scalarmult_curve25519_athlon_scale
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fldl 0(%esp)
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fmull 16(%edx)
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faddp %st(0),%st(1)
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fldl 8(%edx)
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fmul %st(0),%st(0)
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faddp %st(0),%st(1)
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faddp %st(0),%st(1)
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fldl crypto_scalarmult_curve25519_athlon_alpha77
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fadd %st(1),%st(0)
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fsubl crypto_scalarmult_curve25519_athlon_alpha77
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fsubr %st(0),%st(1)
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fxch %st(2)
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fstpl 0(%ecx)
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fldl 32(%esp)
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fmull 72(%edx)
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fldl 40(%esp)
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fmull 64(%edx)
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faddp %st(0),%st(1)
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fldl 48(%esp)
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fmull 56(%edx)
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faddp %st(0),%st(1)
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fmull crypto_scalarmult_curve25519_athlon_scale
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fldl 0(%esp)
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fmull 24(%edx)
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faddp %st(0),%st(1)
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fldl 8(%esp)
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fmull 16(%edx)
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faddp %st(0),%st(1)
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faddp %st(0),%st(2)
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fldl crypto_scalarmult_curve25519_athlon_alpha102
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fadd %st(2),%st(0)
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fsubl crypto_scalarmult_curve25519_athlon_alpha102
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fsubr %st(0),%st(2)
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fxch %st(3)
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fstpl 8(%ecx)
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fldl 40(%esp)
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fmull 72(%edx)
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fldl 48(%esp)
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fmull 64(%edx)
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faddp %st(0),%st(1)
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fldl 56(%edx)
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fmul %st(0),%st(0)
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faddp %st(0),%st(1)
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fmull crypto_scalarmult_curve25519_athlon_scale
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fldl 0(%esp)
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fmull 32(%edx)
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faddp %st(0),%st(1)
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fldl 8(%esp)
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fmull 24(%edx)
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faddp %st(0),%st(1)
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fldl 16(%edx)
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fmul %st(0),%st(0)
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faddp %st(0),%st(1)
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faddp %st(0),%st(3)
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fldl crypto_scalarmult_curve25519_athlon_alpha128
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fadd %st(3),%st(0)
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fsubl crypto_scalarmult_curve25519_athlon_alpha128
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fsubr %st(0),%st(3)
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fxch %st(1)
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fstpl 16(%ecx)
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fldl 48(%esp)
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fldl 72(%edx)
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fmul %st(0),%st(1)
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fmul %st(5),%st(0)
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fxch %st(5)
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fmull 64(%edx)
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faddp %st(0),%st(1)
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fmull crypto_scalarmult_curve25519_athlon_scale
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fldl 0(%esp)
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fmull 40(%edx)
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faddp %st(0),%st(1)
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fldl 8(%esp)
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fmull 32(%edx)
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faddp %st(0),%st(1)
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fldl 16(%esp)
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fmull 24(%edx)
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faddp %st(0),%st(1)
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faddp %st(0),%st(1)
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fldl crypto_scalarmult_curve25519_athlon_alpha153
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fadd %st(1),%st(0)
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fsubl crypto_scalarmult_curve25519_athlon_alpha153
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fsubr %st(0),%st(1)
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fxch %st(2)
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fstpl 24(%ecx)
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fldl 64(%edx)
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fmul %st(0),%st(0)
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faddp %st(0),%st(4)
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fxch %st(3)
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fmull crypto_scalarmult_curve25519_athlon_scale
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fldl 0(%esp)
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fmull 48(%edx)
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faddp %st(0),%st(1)
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fldl 8(%esp)
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fmull 40(%edx)
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faddp %st(0),%st(1)
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fldl 16(%esp)
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fmull 32(%edx)
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faddp %st(0),%st(1)
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fldl 24(%edx)
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fmul %st(0),%st(0)
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faddp %st(0),%st(1)
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faddp %st(0),%st(1)
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fldl crypto_scalarmult_curve25519_athlon_alpha179
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fadd %st(1),%st(0)
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fsubl crypto_scalarmult_curve25519_athlon_alpha179
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fsubr %st(0),%st(1)
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fldl 64(%edx)
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fadd %st(0),%st(0)
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fmull 72(%edx)
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fmull crypto_scalarmult_curve25519_athlon_scale
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fldl 0(%esp)
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fmull 56(%edx)
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faddp %st(0),%st(1)
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fldl 8(%esp)
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fmull 48(%edx)
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faddp %st(0),%st(1)
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fldl 16(%esp)
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fmull 40(%edx)
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faddp %st(0),%st(1)
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fldl 24(%esp)
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fmull 32(%edx)
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faddp %st(0),%st(1)
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faddp %st(0),%st(1)
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fldl crypto_scalarmult_curve25519_athlon_alpha204
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fadd %st(1),%st(0)
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fsubl crypto_scalarmult_curve25519_athlon_alpha204
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fsubr %st(0),%st(1)
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fldl 64(%ecx)
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faddp %st(0),%st(1)
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fldl crypto_scalarmult_curve25519_athlon_alpha230
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fadd %st(1),%st(0)
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fldl 72(%ecx)
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fxch %st(1)
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fsubl crypto_scalarmult_curve25519_athlon_alpha230
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fsubr %st(0),%st(2)
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faddp %st(0),%st(1)
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fxch %st(4)
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fstpl 32(%ecx)
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fxch %st(4)
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fstpl 40(%ecx)
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fxch %st(1)
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fstpl 48(%ecx)
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fstpl 56(%ecx)
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fxch %st(1)
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fstpl 64(%ecx)
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fstpl 72(%ecx)
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add %eax,%esp
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ret
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