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https://github.com/openwrt/openwrt.git
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137 lines
3.9 KiB
Diff
137 lines
3.9 KiB
Diff
From 8563991026ee98bb5e477167236972a45dfea0e3 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Mon, 21 Jan 2013 18:25:59 +0100
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Subject: [PATCH 01/14] MIPS: ralink: adds include files
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Before we start adding the platform code we add the common include files.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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Patchwork: http://patchwork.linux-mips.org/patch/4893/
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---
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arch/mips/include/asm/mach-ralink/ralink_regs.h | 39 ++++++++++++++++++++
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arch/mips/include/asm/mach-ralink/war.h | 25 +++++++++++++
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arch/mips/ralink/common.h | 44 +++++++++++++++++++++++
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3 files changed, 108 insertions(+)
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create mode 100644 arch/mips/include/asm/mach-ralink/ralink_regs.h
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create mode 100644 arch/mips/include/asm/mach-ralink/war.h
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create mode 100644 arch/mips/ralink/common.h
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--- /dev/null
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+++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h
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@@ -0,0 +1,39 @@
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+/*
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+ * Ralink SoC register definitions
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+ *
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+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
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+ * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
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+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ */
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+
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+#ifndef _RALINK_REGS_H_
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+#define _RALINK_REGS_H_
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+
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+extern __iomem void *rt_sysc_membase;
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+extern __iomem void *rt_memc_membase;
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+
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+static inline void rt_sysc_w32(u32 val, unsigned reg)
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+{
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+ __raw_writel(val, rt_sysc_membase + reg);
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+}
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+
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+static inline u32 rt_sysc_r32(unsigned reg)
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+{
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+ return __raw_readl(rt_sysc_membase + reg);
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+}
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+
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+static inline void rt_memc_w32(u32 val, unsigned reg)
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+{
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+ __raw_writel(val, rt_memc_membase + reg);
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+}
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+
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+static inline u32 rt_memc_r32(unsigned reg)
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+{
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+ return __raw_readl(rt_memc_membase + reg);
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+}
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+
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+#endif /* _RALINK_REGS_H_ */
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--- /dev/null
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+++ b/arch/mips/include/asm/mach-ralink/war.h
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@@ -0,0 +1,25 @@
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+/*
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+ * This file is subject to the terms and conditions of the GNU General Public
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+ * License. See the file "COPYING" in the main directory of this archive
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+ * for more details.
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+ *
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+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
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+ */
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+#ifndef __ASM_MACH_RALINK_WAR_H
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+#define __ASM_MACH_RALINK_WAR_H
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+
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+#define R4600_V1_INDEX_ICACHEOP_WAR 0
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+#define R4600_V1_HIT_CACHEOP_WAR 0
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+#define R4600_V2_HIT_CACHEOP_WAR 0
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+#define R5432_CP0_INTERRUPT_WAR 0
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+#define BCM1250_M3_WAR 0
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+#define SIBYTE_1956_WAR 0
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+#define MIPS4K_ICACHE_REFILL_WAR 0
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+#define MIPS_CACHE_SYNC_WAR 0
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+#define TX49XX_ICACHE_INDEX_INV_WAR 0
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+#define RM9000_CDEX_SMP_WAR 0
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+#define ICACHE_REFILLS_WORKAROUND_WAR 0
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+#define R10000_LLSC_WAR 0
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+#define MIPS34K_MISSED_ITLB_WAR 0
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+
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+#endif /* __ASM_MACH_RALINK_WAR_H */
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--- /dev/null
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+++ b/arch/mips/ralink/common.h
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@@ -0,0 +1,44 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ *
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+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
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+ */
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+
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+#ifndef _RALINK_COMMON_H__
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+#define _RALINK_COMMON_H__
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+
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+#define RAMIPS_SYS_TYPE_LEN 32
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+
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+struct ralink_pinmux_grp {
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+ const char *name;
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+ u32 mask;
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+ int gpio_first;
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+ int gpio_last;
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+};
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+
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+struct ralink_pinmux {
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+ struct ralink_pinmux_grp *mode;
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+ struct ralink_pinmux_grp *uart;
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+ int uart_shift;
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+ void (*wdt_reset)(void);
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+};
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+extern struct ralink_pinmux gpio_pinmux;
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+
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+struct ralink_soc_info {
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+ unsigned char sys_type[RAMIPS_SYS_TYPE_LEN];
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+ unsigned char *compatible;
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+};
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+extern struct ralink_soc_info soc_info;
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+
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+extern void ralink_of_remap(void);
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+
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+extern void ralink_clk_init(void);
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+extern void ralink_clk_add(const char *dev, unsigned long rate);
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+
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+extern void prom_soc_init(struct ralink_soc_info *soc_info);
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+
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+__iomem void *plat_of_remap_node(const char *node);
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+
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+#endif /* _RALINK_COMMON_H__ */
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