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58 lines
2.3 KiB
Diff
58 lines
2.3 KiB
Diff
From 2f2d389efda4caa4c1b69cb4fa2ab217f0fe6d6f Mon Sep 17 00:00:00 2001
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From: Chi-Hsien Lin <Chi-Hsien.Lin@cypress.com>
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Date: Wed, 21 Nov 2018 07:53:50 +0000
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Subject: [PATCH] brcmfmac: 4373 save-restore support
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Use chipcommon sr_control0 register to check 4373 sr support.
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Reviewed-by: Arend van Spriel <arend.vanspriel@broadcom.com>
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Signed-off-by: Chi-Hsien Lin <chi-hsien.lin@cypress.com>
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Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
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---
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.../broadcom/brcm80211/brcmfmac/chip.c | 5 +++++
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.../broadcom/brcm80211/include/chipcommon.h | 19 +++++++++++++++++++
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2 files changed, 24 insertions(+)
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--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c
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+++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c
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@@ -1365,6 +1365,11 @@ bool brcmf_chip_sr_capable(struct brcmf_
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addr = CORE_CC_REG(base, sr_control1);
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reg = chip->ops->read32(chip->ctx, addr);
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return reg != 0;
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+ case CY_CC_4373_CHIP_ID:
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+ /* explicitly check SR engine enable bit */
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+ addr = CORE_CC_REG(base, sr_control0);
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+ reg = chip->ops->read32(chip->ctx, addr);
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+ return (reg & CC_SR_CTL0_ENABLE_MASK) != 0;
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case CY_CC_43012_CHIP_ID:
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addr = CORE_CC_REG(pmu->base, retention_ctl);
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reg = chip->ops->read32(chip->ctx, addr);
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--- a/drivers/net/wireless/broadcom/brcm80211/include/chipcommon.h
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+++ b/drivers/net/wireless/broadcom/brcm80211/include/chipcommon.h
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@@ -269,6 +269,25 @@ struct chipcregs {
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/* GSIO (spi/i2c) present, rev >= 37 */
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#define CC_CAP2_GSIO 0x00000002
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+/* sr_control0, rev >= 48 */
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+#define CC_SR_CTL0_ENABLE_MASK BIT(0)
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+#define CC_SR_CTL0_ENABLE_SHIFT 0
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+#define CC_SR_CTL0_EN_SR_ENG_CLK_SHIFT 1 /* sr_clk to sr_memory enable */
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+#define CC_SR_CTL0_RSRC_TRIGGER_SHIFT 2 /* Rising edge resource trigger 0 to
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+ * sr_engine
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+ */
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+#define CC_SR_CTL0_MIN_DIV_SHIFT 6 /* Min division value for fast clk
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+ * in sr_engine
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+ */
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+#define CC_SR_CTL0_EN_SBC_STBY_SHIFT 16
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+#define CC_SR_CTL0_EN_SR_ALP_CLK_MASK_SHIFT 18
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+#define CC_SR_CTL0_EN_SR_HT_CLK_SHIFT 19
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+#define CC_SR_CTL0_ALLOW_PIC_SHIFT 20 /* Allow pic to separate power
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+ * domains
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+ */
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+#define CC_SR_CTL0_MAX_SR_LQ_CLK_CNT_SHIFT 25
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+#define CC_SR_CTL0_EN_MEM_DISABLE_FOR_SLEEP 30
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+
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/* pmucapabilities */
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#define PCAP_REV_MASK 0x000000ff
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#define PCAP_RC_MASK 0x00001f00
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