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ff08b09570
All (still relevant) patches were refresh. The following patches were dropped because they are applied upstream: - 0003-MIPS-lantiq-handle-vmmc-memory-reservation.patch - 0005-MIPS-lantiq-add-reset-controller-api-support.patch - 0006-MIPS-lantiq-reboot-gphy-on-restart.patch - 0009-MIPS-lantiq-command-line-work-around.patch - 0010-MIPS-lantiq-export-soc-type.patch - 0011-lantiq-add-support-for-xrx200-firmware-depending-on-.patch - 0037-MIPS-lantiq-move-eiu-init-after-irq_domain-register.patch Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> SVN-Revision: 46216
272 lines
8.2 KiB
Diff
272 lines
8.2 KiB
Diff
From 0a63ab263725c427051a8bbaa0732b749627da27 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Thu, 7 Aug 2014 18:15:36 +0200
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Subject: [PATCH 23/36] NET: PHY: adds driver for lantiq PHY11G
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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drivers/net/phy/Kconfig | 5 +
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drivers/net/phy/Makefile | 1 +
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drivers/net/phy/lantiq.c | 231 ++++++++++++++++++++++++++++++++++++++++++++++
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3 files changed, 237 insertions(+)
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create mode 100644 drivers/net/phy/lantiq.c
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--- a/drivers/net/phy/Kconfig
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+++ b/drivers/net/phy/Kconfig
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@@ -165,6 +165,11 @@ config RTL8306_PHY
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tristate "Driver for Realtek RTL8306S switches"
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select SWCONFIG
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+config LANTIQ_PHY
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+ tristate "Driver for Lantiq PHYs"
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+ ---help---
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+ Supports the 11G and 22E PHYs.
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+
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config FIXED_PHY
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tristate "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs"
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depends on PHYLIB
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--- a/drivers/net/phy/Makefile
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+++ b/drivers/net/phy/Makefile
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@@ -40,6 +40,7 @@ obj-$(CONFIG_NATIONAL_PHY) += national.o
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obj-$(CONFIG_DP83640_PHY) += dp83640.o
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obj-$(CONFIG_STE10XP) += ste10Xp.o
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obj-$(CONFIG_MICREL_PHY) += micrel.o
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+obj-$(CONFIG_LANTIQ_PHY) += lantiq.o
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obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o
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obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o
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obj-$(CONFIG_AT803X_PHY) += at803x.o
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--- /dev/null
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+++ b/drivers/net/phy/lantiq.c
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@@ -0,0 +1,231 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; either version 2 of the License, or
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+ * (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
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+ *
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+ * Copyright (C) 2012 Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
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+ */
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+
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+#include <linux/module.h>
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+#include <linux/phy.h>
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+
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+#define MII_MMDCTRL 0x0d
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+#define MII_MMDDATA 0x0e
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+
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+#define MII_VR9_11G_IMASK 0x19 /* interrupt mask */
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+#define MII_VR9_11G_ISTAT 0x1a /* interrupt status */
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+
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+#define INT_VR9_11G_WOL BIT(15) /* Wake-On-LAN */
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+#define INT_VR9_11G_ANE BIT(11) /* Auto-Neg error */
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+#define INT_VR9_11G_ANC BIT(10) /* Auto-Neg complete */
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+#define INT_VR9_11G_ADSC BIT(5) /* Link auto-downspeed detect */
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+#define INT_VR9_11G_DXMC BIT(2) /* Duplex mode change */
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+#define INT_VR9_11G_LSPC BIT(1) /* Link speed change */
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+#define INT_VR9_11G_LSTC BIT(0) /* Link state change */
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+#define INT_VR9_11G_MASK (INT_VR9_11G_LSTC | INT_VR9_11G_ADSC)
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+
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+#define ADVERTISED_MPD BIT(10) /* Multi-port device */
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+
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+#define MMD_DEVAD 0x1f
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+#define MMD_ACTYPE_SHIFT 14
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+#define MMD_ACTYPE_ADDRESS (0 << MMD_ACTYPE_SHIFT)
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+#define MMD_ACTYPE_DATA (1 << MMD_ACTYPE_SHIFT)
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+#define MMD_ACTYPE_DATA_PI (2 << MMD_ACTYPE_SHIFT)
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+#define MMD_ACTYPE_DATA_PIWR (3 << MMD_ACTYPE_SHIFT)
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+
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+static __maybe_unused int vr9_gphy_mmd_read(struct phy_device *phydev,
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+ u16 regnum)
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+{
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+ phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_ADDRESS | MMD_DEVAD);
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+ phy_write(phydev, MII_MMDDATA, regnum);
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+ phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_DATA | MMD_DEVAD);
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+
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+ return phy_read(phydev, MII_MMDDATA);
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+}
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+
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+static __maybe_unused int vr9_gphy_mmd_write(struct phy_device *phydev,
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+ u16 regnum, u16 val)
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+{
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+ phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_ADDRESS | MMD_DEVAD);
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+ phy_write(phydev, MII_MMDDATA, regnum);
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+ phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_DATA | MMD_DEVAD);
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+ phy_write(phydev, MII_MMDDATA, val);
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+
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+ return 0;
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+}
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+
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+static int vr9_gphy_config_init(struct phy_device *phydev)
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+{
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+ int err;
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+
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+ dev_dbg(&phydev->dev, "%s\n", __func__);
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+
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+ /* Mask all interrupts */
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+ err = phy_write(phydev, MII_VR9_11G_IMASK, 0);
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+ if (err)
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+ return err;
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+
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+ /* Clear all pending interrupts */
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+ phy_read(phydev, MII_VR9_11G_ISTAT);
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+
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+ vr9_gphy_mmd_write(phydev, 0x1e0, 0xc5);
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+ vr9_gphy_mmd_write(phydev, 0x1e1, 0x67);
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+ vr9_gphy_mmd_write(phydev, 0x1e2, 0x42);
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+ vr9_gphy_mmd_write(phydev, 0x1e3, 0x10);
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+ vr9_gphy_mmd_write(phydev, 0x1e4, 0x70);
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+ vr9_gphy_mmd_write(phydev, 0x1e5, 0x03);
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+ vr9_gphy_mmd_write(phydev, 0x1e6, 0x20);
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+ vr9_gphy_mmd_write(phydev, 0x1e7, 0x00);
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+ vr9_gphy_mmd_write(phydev, 0x1e8, 0x40);
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+ vr9_gphy_mmd_write(phydev, 0x1e9, 0x20);
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+
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+ return 0;
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+}
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+
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+static int vr9_gphy_config_aneg(struct phy_device *phydev)
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+{
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+ int reg, err;
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+
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+ /* Advertise as multi-port device */
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+ reg = phy_read(phydev, MII_CTRL1000);
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+ reg |= ADVERTISED_MPD;
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+ err = phy_write(phydev, MII_CTRL1000, reg);
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+ if (err)
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+ return err;
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+
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+ return genphy_config_aneg(phydev);
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+}
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+
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+static int vr9_gphy_ack_interrupt(struct phy_device *phydev)
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+{
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+ int reg;
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+
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+ /*
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+ * Possible IRQ numbers:
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+ * - IM3_IRL18 for GPHY0
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+ * - IM3_IRL17 for GPHY1
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+ *
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+ * Due to a silicon bug IRQ lines are not really independent from
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+ * each other. Sometimes the two lines are driven at the same time
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+ * if only one GPHY core raises the interrupt.
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+ */
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+
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+ reg = phy_read(phydev, MII_VR9_11G_ISTAT);
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+
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+ return (reg < 0) ? reg : 0;
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+}
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+
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+static int vr9_gphy_did_interrupt(struct phy_device *phydev)
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+{
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+ int reg;
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+
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+ reg = phy_read(phydev, MII_VR9_11G_ISTAT);
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+
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+ return reg > 0;
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+}
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+
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+static int vr9_gphy_config_intr(struct phy_device *phydev)
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+{
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+ int err;
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+
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+ if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
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+ err = phy_write(phydev, MII_VR9_11G_IMASK, INT_VR9_11G_MASK);
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+ else
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+ err = phy_write(phydev, MII_VR9_11G_IMASK, 0);
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+
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+ return err;
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+}
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+
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+static struct phy_driver lantiq_phy[] = {
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+ {
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+ .phy_id = 0xd565a400,
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+ .phy_id_mask = 0xffffffff,
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+ .name = "Lantiq XWAY PEF7071",
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+ .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
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+ .flags = 0, /*PHY_HAS_INTERRUPT,*/
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+ .config_init = vr9_gphy_config_init,
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+ .config_aneg = vr9_gphy_config_aneg,
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+ .read_status = genphy_read_status,
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+ .ack_interrupt = vr9_gphy_ack_interrupt,
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+ .did_interrupt = vr9_gphy_did_interrupt,
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+ .config_intr = vr9_gphy_config_intr,
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+ .driver = { .owner = THIS_MODULE },
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+ }, {
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+ .phy_id = 0x030260D0,
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+ .phy_id_mask = 0xfffffff0,
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+ .name = "Lantiq XWAY VR9 GPHY 11G v1.3",
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+ .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
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+ .flags = 0, /*PHY_HAS_INTERRUPT,*/
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+ .config_init = vr9_gphy_config_init,
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+ .config_aneg = vr9_gphy_config_aneg,
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+ .read_status = genphy_read_status,
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+ .ack_interrupt = vr9_gphy_ack_interrupt,
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+ .did_interrupt = vr9_gphy_did_interrupt,
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+ .config_intr = vr9_gphy_config_intr,
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+ .driver = { .owner = THIS_MODULE },
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+ }, {
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+ .phy_id = 0xd565a408,
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+ .phy_id_mask = 0xfffffff8,
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+ .name = "Lantiq XWAY VR9 GPHY 11G v1.4",
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+ .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
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+ .flags = 0, /*PHY_HAS_INTERRUPT,*/
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+ .config_init = vr9_gphy_config_init,
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+ .config_aneg = vr9_gphy_config_aneg,
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+ .read_status = genphy_read_status,
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+ .ack_interrupt = vr9_gphy_ack_interrupt,
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+ .did_interrupt = vr9_gphy_did_interrupt,
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+ .config_intr = vr9_gphy_config_intr,
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+ .driver = { .owner = THIS_MODULE },
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+ }, {
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+ .phy_id = 0xd565a418,
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+ .phy_id_mask = 0xfffffff8,
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+ .name = "Lantiq XWAY XRX PHY22F v1.4",
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+ .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
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+ .flags = 0, /*PHY_HAS_INTERRUPT,*/
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+ .config_init = vr9_gphy_config_init,
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+ .config_aneg = vr9_gphy_config_aneg,
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+ .read_status = genphy_read_status,
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+ .ack_interrupt = vr9_gphy_ack_interrupt,
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+ .did_interrupt = vr9_gphy_did_interrupt,
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+ .config_intr = vr9_gphy_config_intr,
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+ .driver = { .owner = THIS_MODULE },
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+ },
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+};
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+
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+static int __init ltq_phy_init(void)
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+{
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+ int i;
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+
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+ for (i = 0; i < ARRAY_SIZE(lantiq_phy); i++) {
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+ int err = phy_driver_register(&lantiq_phy[i]);
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+ if (err)
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+ pr_err("lantiq_phy: failed to load %s\n", lantiq_phy[i].name);
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+ }
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+
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+ return 0;
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+}
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+
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+static void __exit ltq_phy_exit(void)
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+{
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+ int i;
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+
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+ for (i = 0; i < ARRAY_SIZE(lantiq_phy); i++)
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+ phy_driver_unregister(&lantiq_phy[i]);
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+}
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+
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+module_init(ltq_phy_init);
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+module_exit(ltq_phy_exit);
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+
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+MODULE_DESCRIPTION("Lantiq PHY drivers");
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+MODULE_AUTHOR("Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>");
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+MODULE_LICENSE("GPL");
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