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https://github.com/openwrt/openwrt.git
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e842e16f45
- Refresh all patches - Removed upstreamed - Adapted 1 Compile tested on: bcm53xx, cns3xxx, imx6, lantiq Run tested on: cns3xxx & imx6 Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com> [update from 4.9.28 to 4.9.29] Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
487 lines
13 KiB
Diff
487 lines
13 KiB
Diff
From 6078c651947a148c1de543b54fe55af43a63043a Mon Sep 17 00:00:00 2001
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From: James Liao <jamesjj.liao@mediatek.com>
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Date: Thu, 20 Oct 2016 16:56:35 +0800
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Subject: [PATCH 1/2] soc: mediatek: Refine scpsys to support multiple platform
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Refine scpsys driver common code to support multiple SoC / platform.
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Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
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Reviewed-by: Kevin Hilman <khilman@baylibre.com>
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Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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---
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drivers/soc/mediatek/mtk-scpsys.c | 348 +++++++++++++++++++++++---------------
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1 file changed, 210 insertions(+), 138 deletions(-)
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--- a/drivers/soc/mediatek/mtk-scpsys.c
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+++ b/drivers/soc/mediatek/mtk-scpsys.c
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@@ -11,17 +11,15 @@
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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-#include <linux/delay.h>
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+#include <linux/init.h>
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#include <linux/io.h>
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-#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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-#include <linux/init.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_domain.h>
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-#include <linux/regmap.h>
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-#include <linux/soc/mediatek/infracfg.h>
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#include <linux/regulator/consumer.h>
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+#include <linux/soc/mediatek/infracfg.h>
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+
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#include <dt-bindings/power/mt8173-power.h>
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#define SPM_VDE_PWR_CON 0x0210
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@@ -34,6 +32,7 @@
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#define SPM_MFG_2D_PWR_CON 0x02c0
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#define SPM_MFG_ASYNC_PWR_CON 0x02c4
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#define SPM_USB_PWR_CON 0x02cc
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+
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#define SPM_PWR_STATUS 0x060c
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#define SPM_PWR_STATUS_2ND 0x0610
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@@ -55,12 +54,21 @@
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#define PWR_STATUS_USB BIT(25)
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enum clk_id {
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- MT8173_CLK_NONE,
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- MT8173_CLK_MM,
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- MT8173_CLK_MFG,
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- MT8173_CLK_VENC,
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- MT8173_CLK_VENC_LT,
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- MT8173_CLK_MAX,
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+ CLK_NONE,
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+ CLK_MM,
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+ CLK_MFG,
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+ CLK_VENC,
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+ CLK_VENC_LT,
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+ CLK_MAX,
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+};
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+
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+static const char * const clk_names[] = {
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+ NULL,
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+ "mm",
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+ "mfg",
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+ "venc",
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+ "venc_lt",
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+ NULL,
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};
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#define MAX_CLKS 2
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@@ -76,98 +84,6 @@ struct scp_domain_data {
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bool active_wakeup;
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};
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-static const struct scp_domain_data scp_domain_data[] = {
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- [MT8173_POWER_DOMAIN_VDEC] = {
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- .name = "vdec",
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- .sta_mask = PWR_STATUS_VDEC,
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- .ctl_offs = SPM_VDE_PWR_CON,
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- .sram_pdn_bits = GENMASK(11, 8),
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- .sram_pdn_ack_bits = GENMASK(12, 12),
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- .clk_id = {MT8173_CLK_MM},
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- },
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- [MT8173_POWER_DOMAIN_VENC] = {
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- .name = "venc",
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- .sta_mask = PWR_STATUS_VENC,
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- .ctl_offs = SPM_VEN_PWR_CON,
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- .sram_pdn_bits = GENMASK(11, 8),
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- .sram_pdn_ack_bits = GENMASK(15, 12),
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- .clk_id = {MT8173_CLK_MM, MT8173_CLK_VENC},
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- },
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- [MT8173_POWER_DOMAIN_ISP] = {
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- .name = "isp",
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- .sta_mask = PWR_STATUS_ISP,
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- .ctl_offs = SPM_ISP_PWR_CON,
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- .sram_pdn_bits = GENMASK(11, 8),
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- .sram_pdn_ack_bits = GENMASK(13, 12),
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- .clk_id = {MT8173_CLK_MM},
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- },
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- [MT8173_POWER_DOMAIN_MM] = {
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- .name = "mm",
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- .sta_mask = PWR_STATUS_DISP,
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- .ctl_offs = SPM_DIS_PWR_CON,
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- .sram_pdn_bits = GENMASK(11, 8),
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- .sram_pdn_ack_bits = GENMASK(12, 12),
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- .clk_id = {MT8173_CLK_MM},
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- .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
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- MT8173_TOP_AXI_PROT_EN_MM_M1,
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- },
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- [MT8173_POWER_DOMAIN_VENC_LT] = {
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- .name = "venc_lt",
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- .sta_mask = PWR_STATUS_VENC_LT,
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- .ctl_offs = SPM_VEN2_PWR_CON,
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- .sram_pdn_bits = GENMASK(11, 8),
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- .sram_pdn_ack_bits = GENMASK(15, 12),
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- .clk_id = {MT8173_CLK_MM, MT8173_CLK_VENC_LT},
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- },
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- [MT8173_POWER_DOMAIN_AUDIO] = {
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- .name = "audio",
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- .sta_mask = PWR_STATUS_AUDIO,
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- .ctl_offs = SPM_AUDIO_PWR_CON,
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- .sram_pdn_bits = GENMASK(11, 8),
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- .sram_pdn_ack_bits = GENMASK(15, 12),
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- .clk_id = {MT8173_CLK_NONE},
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- },
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- [MT8173_POWER_DOMAIN_USB] = {
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- .name = "usb",
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- .sta_mask = PWR_STATUS_USB,
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- .ctl_offs = SPM_USB_PWR_CON,
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- .sram_pdn_bits = GENMASK(11, 8),
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- .sram_pdn_ack_bits = GENMASK(15, 12),
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- .clk_id = {MT8173_CLK_NONE},
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- .active_wakeup = true,
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- },
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- [MT8173_POWER_DOMAIN_MFG_ASYNC] = {
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- .name = "mfg_async",
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- .sta_mask = PWR_STATUS_MFG_ASYNC,
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- .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
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- .sram_pdn_bits = GENMASK(11, 8),
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- .sram_pdn_ack_bits = 0,
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- .clk_id = {MT8173_CLK_MFG},
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- },
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- [MT8173_POWER_DOMAIN_MFG_2D] = {
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- .name = "mfg_2d",
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- .sta_mask = PWR_STATUS_MFG_2D,
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- .ctl_offs = SPM_MFG_2D_PWR_CON,
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- .sram_pdn_bits = GENMASK(11, 8),
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- .sram_pdn_ack_bits = GENMASK(13, 12),
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- .clk_id = {MT8173_CLK_NONE},
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- },
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- [MT8173_POWER_DOMAIN_MFG] = {
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- .name = "mfg",
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- .sta_mask = PWR_STATUS_MFG,
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- .ctl_offs = SPM_MFG_PWR_CON,
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- .sram_pdn_bits = GENMASK(13, 8),
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- .sram_pdn_ack_bits = GENMASK(21, 16),
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- .clk_id = {MT8173_CLK_NONE},
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- .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S |
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- MT8173_TOP_AXI_PROT_EN_MFG_M0 |
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- MT8173_TOP_AXI_PROT_EN_MFG_M1 |
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- MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT,
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- },
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-};
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-
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-#define NUM_DOMAINS ARRAY_SIZE(scp_domain_data)
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-
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struct scp;
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struct scp_domain {
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@@ -179,7 +95,7 @@ struct scp_domain {
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};
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struct scp {
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- struct scp_domain domains[NUM_DOMAINS];
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+ struct scp_domain *domains;
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struct genpd_onecell_data pd_data;
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struct device *dev;
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void __iomem *base;
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@@ -408,57 +324,55 @@ static bool scpsys_active_wakeup(struct
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return scpd->data->active_wakeup;
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}
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-static int scpsys_probe(struct platform_device *pdev)
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+static void init_clks(struct platform_device *pdev, struct clk **clk)
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+{
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+ int i;
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+
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+ for (i = CLK_NONE + 1; i < CLK_MAX; i++)
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+ clk[i] = devm_clk_get(&pdev->dev, clk_names[i]);
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+}
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+
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+static struct scp *init_scp(struct platform_device *pdev,
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+ const struct scp_domain_data *scp_domain_data, int num)
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{
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struct genpd_onecell_data *pd_data;
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struct resource *res;
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- int i, j, ret;
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+ int i, j;
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struct scp *scp;
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- struct clk *clk[MT8173_CLK_MAX];
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+ struct clk *clk[CLK_MAX];
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scp = devm_kzalloc(&pdev->dev, sizeof(*scp), GFP_KERNEL);
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if (!scp)
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- return -ENOMEM;
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+ return ERR_PTR(-ENOMEM);
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scp->dev = &pdev->dev;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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scp->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(scp->base))
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- return PTR_ERR(scp->base);
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+ return ERR_CAST(scp->base);
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+
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+ scp->domains = devm_kzalloc(&pdev->dev,
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+ sizeof(*scp->domains) * num, GFP_KERNEL);
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+ if (!scp->domains)
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+ return ERR_PTR(-ENOMEM);
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pd_data = &scp->pd_data;
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pd_data->domains = devm_kzalloc(&pdev->dev,
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- sizeof(*pd_data->domains) * NUM_DOMAINS, GFP_KERNEL);
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+ sizeof(*pd_data->domains) * num, GFP_KERNEL);
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if (!pd_data->domains)
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- return -ENOMEM;
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-
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- clk[MT8173_CLK_MM] = devm_clk_get(&pdev->dev, "mm");
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- if (IS_ERR(clk[MT8173_CLK_MM]))
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- return PTR_ERR(clk[MT8173_CLK_MM]);
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-
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- clk[MT8173_CLK_MFG] = devm_clk_get(&pdev->dev, "mfg");
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- if (IS_ERR(clk[MT8173_CLK_MFG]))
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- return PTR_ERR(clk[MT8173_CLK_MFG]);
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-
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- clk[MT8173_CLK_VENC] = devm_clk_get(&pdev->dev, "venc");
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- if (IS_ERR(clk[MT8173_CLK_VENC]))
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- return PTR_ERR(clk[MT8173_CLK_VENC]);
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-
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- clk[MT8173_CLK_VENC_LT] = devm_clk_get(&pdev->dev, "venc_lt");
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- if (IS_ERR(clk[MT8173_CLK_VENC_LT]))
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- return PTR_ERR(clk[MT8173_CLK_VENC_LT]);
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+ return ERR_PTR(-ENOMEM);
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scp->infracfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
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"infracfg");
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if (IS_ERR(scp->infracfg)) {
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dev_err(&pdev->dev, "Cannot find infracfg controller: %ld\n",
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PTR_ERR(scp->infracfg));
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- return PTR_ERR(scp->infracfg);
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+ return ERR_CAST(scp->infracfg);
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}
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- for (i = 0; i < NUM_DOMAINS; i++) {
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+ for (i = 0; i < num; i++) {
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struct scp_domain *scpd = &scp->domains[i];
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const struct scp_domain_data *data = &scp_domain_data[i];
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@@ -467,13 +381,15 @@ static int scpsys_probe(struct platform_
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if (PTR_ERR(scpd->supply) == -ENODEV)
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scpd->supply = NULL;
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else
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- return PTR_ERR(scpd->supply);
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+ return ERR_CAST(scpd->supply);
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}
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}
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- pd_data->num_domains = NUM_DOMAINS;
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+ pd_data->num_domains = num;
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+
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+ init_clks(pdev, clk);
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- for (i = 0; i < NUM_DOMAINS; i++) {
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+ for (i = 0; i < num; i++) {
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struct scp_domain *scpd = &scp->domains[i];
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struct generic_pm_domain *genpd = &scpd->genpd;
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const struct scp_domain_data *data = &scp_domain_data[i];
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@@ -482,13 +398,37 @@ static int scpsys_probe(struct platform_
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scpd->scp = scp;
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scpd->data = data;
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- for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++)
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- scpd->clk[j] = clk[data->clk_id[j]];
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+
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+ for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++) {
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+ struct clk *c = clk[data->clk_id[j]];
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+
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+ if (IS_ERR(c)) {
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+ dev_err(&pdev->dev, "%s: clk unavailable\n",
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+ data->name);
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+ return ERR_CAST(c);
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+ }
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+
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+ scpd->clk[j] = c;
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+ }
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genpd->name = data->name;
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genpd->power_off = scpsys_power_off;
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genpd->power_on = scpsys_power_on;
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genpd->dev_ops.active_wakeup = scpsys_active_wakeup;
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+ }
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+
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+ return scp;
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+}
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+
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+static void mtk_register_power_domains(struct platform_device *pdev,
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+ struct scp *scp, int num)
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+{
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+ struct genpd_onecell_data *pd_data;
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+ int i, ret;
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+
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+ for (i = 0; i < num; i++) {
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+ struct scp_domain *scpd = &scp->domains[i];
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+ struct generic_pm_domain *genpd = &scpd->genpd;
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/*
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* Initially turn on all domains to make the domains usable
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@@ -507,6 +447,123 @@ static int scpsys_probe(struct platform_
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* valid.
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*/
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+ pd_data = &scp->pd_data;
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+
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+ ret = of_genpd_add_provider_onecell(pdev->dev.of_node, pd_data);
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+ if (ret)
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+ dev_err(&pdev->dev, "Failed to add OF provider: %d\n", ret);
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+}
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+
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+/*
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+ * MT8173 power domain support
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+ */
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+
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+static const struct scp_domain_data scp_domain_data_mt8173[] = {
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+ [MT8173_POWER_DOMAIN_VDEC] = {
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+ .name = "vdec",
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+ .sta_mask = PWR_STATUS_VDEC,
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+ .ctl_offs = SPM_VDE_PWR_CON,
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+ .sram_pdn_bits = GENMASK(11, 8),
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+ .sram_pdn_ack_bits = GENMASK(12, 12),
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+ .clk_id = {CLK_MM},
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+ },
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+ [MT8173_POWER_DOMAIN_VENC] = {
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+ .name = "venc",
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+ .sta_mask = PWR_STATUS_VENC,
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+ .ctl_offs = SPM_VEN_PWR_CON,
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+ .sram_pdn_bits = GENMASK(11, 8),
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+ .sram_pdn_ack_bits = GENMASK(15, 12),
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+ .clk_id = {CLK_MM, CLK_VENC},
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+ },
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+ [MT8173_POWER_DOMAIN_ISP] = {
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+ .name = "isp",
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+ .sta_mask = PWR_STATUS_ISP,
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+ .ctl_offs = SPM_ISP_PWR_CON,
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+ .sram_pdn_bits = GENMASK(11, 8),
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+ .sram_pdn_ack_bits = GENMASK(13, 12),
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+ .clk_id = {CLK_MM},
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+ },
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+ [MT8173_POWER_DOMAIN_MM] = {
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+ .name = "mm",
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+ .sta_mask = PWR_STATUS_DISP,
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+ .ctl_offs = SPM_DIS_PWR_CON,
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+ .sram_pdn_bits = GENMASK(11, 8),
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+ .sram_pdn_ack_bits = GENMASK(12, 12),
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+ .clk_id = {CLK_MM},
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+ .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
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+ MT8173_TOP_AXI_PROT_EN_MM_M1,
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+ },
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+ [MT8173_POWER_DOMAIN_VENC_LT] = {
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+ .name = "venc_lt",
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+ .sta_mask = PWR_STATUS_VENC_LT,
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+ .ctl_offs = SPM_VEN2_PWR_CON,
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+ .sram_pdn_bits = GENMASK(11, 8),
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+ .sram_pdn_ack_bits = GENMASK(15, 12),
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+ .clk_id = {CLK_MM, CLK_VENC_LT},
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+ },
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+ [MT8173_POWER_DOMAIN_AUDIO] = {
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+ .name = "audio",
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+ .sta_mask = PWR_STATUS_AUDIO,
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+ .ctl_offs = SPM_AUDIO_PWR_CON,
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+ .sram_pdn_bits = GENMASK(11, 8),
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+ .sram_pdn_ack_bits = GENMASK(15, 12),
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+ .clk_id = {CLK_NONE},
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+ },
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+ [MT8173_POWER_DOMAIN_USB] = {
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+ .name = "usb",
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+ .sta_mask = PWR_STATUS_USB,
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+ .ctl_offs = SPM_USB_PWR_CON,
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+ .sram_pdn_bits = GENMASK(11, 8),
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+ .sram_pdn_ack_bits = GENMASK(15, 12),
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+ .clk_id = {CLK_NONE},
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+ .active_wakeup = true,
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+ },
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+ [MT8173_POWER_DOMAIN_MFG_ASYNC] = {
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+ .name = "mfg_async",
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+ .sta_mask = PWR_STATUS_MFG_ASYNC,
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+ .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
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+ .sram_pdn_bits = GENMASK(11, 8),
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+ .sram_pdn_ack_bits = 0,
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+ .clk_id = {CLK_MFG},
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+ },
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+ [MT8173_POWER_DOMAIN_MFG_2D] = {
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+ .name = "mfg_2d",
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+ .sta_mask = PWR_STATUS_MFG_2D,
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+ .ctl_offs = SPM_MFG_2D_PWR_CON,
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+ .sram_pdn_bits = GENMASK(11, 8),
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|
+ .sram_pdn_ack_bits = GENMASK(13, 12),
|
|
+ .clk_id = {CLK_NONE},
|
|
+ },
|
|
+ [MT8173_POWER_DOMAIN_MFG] = {
|
|
+ .name = "mfg",
|
|
+ .sta_mask = PWR_STATUS_MFG,
|
|
+ .ctl_offs = SPM_MFG_PWR_CON,
|
|
+ .sram_pdn_bits = GENMASK(13, 8),
|
|
+ .sram_pdn_ack_bits = GENMASK(21, 16),
|
|
+ .clk_id = {CLK_NONE},
|
|
+ .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S |
|
|
+ MT8173_TOP_AXI_PROT_EN_MFG_M0 |
|
|
+ MT8173_TOP_AXI_PROT_EN_MFG_M1 |
|
|
+ MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT,
|
|
+ },
|
|
+};
|
|
+
|
|
+#define NUM_DOMAINS_MT8173 ARRAY_SIZE(scp_domain_data_mt8173)
|
|
+
|
|
+static int __init scpsys_probe_mt8173(struct platform_device *pdev)
|
|
+{
|
|
+ struct scp *scp;
|
|
+ struct genpd_onecell_data *pd_data;
|
|
+ int ret;
|
|
+
|
|
+ scp = init_scp(pdev, scp_domain_data_mt8173, NUM_DOMAINS_MT8173);
|
|
+ if (IS_ERR(scp))
|
|
+ return PTR_ERR(scp);
|
|
+
|
|
+ mtk_register_power_domains(pdev, scp, NUM_DOMAINS_MT8173);
|
|
+
|
|
+ pd_data = &scp->pd_data;
|
|
+
|
|
ret = pm_genpd_add_subdomain(pd_data->domains[MT8173_POWER_DOMAIN_MFG_ASYNC],
|
|
pd_data->domains[MT8173_POWER_DOMAIN_MFG_2D]);
|
|
if (ret && IS_ENABLED(CONFIG_PM))
|
|
@@ -517,21 +574,36 @@ static int scpsys_probe(struct platform_
|
|
if (ret && IS_ENABLED(CONFIG_PM))
|
|
dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret);
|
|
|
|
- ret = of_genpd_add_provider_onecell(pdev->dev.of_node, pd_data);
|
|
- if (ret)
|
|
- dev_err(&pdev->dev, "Failed to add OF provider: %d\n", ret);
|
|
-
|
|
return 0;
|
|
}
|
|
|
|
+/*
|
|
+ * scpsys driver init
|
|
+ */
|
|
+
|
|
static const struct of_device_id of_scpsys_match_tbl[] = {
|
|
{
|
|
.compatible = "mediatek,mt8173-scpsys",
|
|
+ .data = scpsys_probe_mt8173,
|
|
}, {
|
|
/* sentinel */
|
|
}
|
|
};
|
|
|
|
+static int scpsys_probe(struct platform_device *pdev)
|
|
+{
|
|
+ int (*probe)(struct platform_device *);
|
|
+ const struct of_device_id *of_id;
|
|
+
|
|
+ of_id = of_match_node(of_scpsys_match_tbl, pdev->dev.of_node);
|
|
+ if (!of_id || !of_id->data)
|
|
+ return -EINVAL;
|
|
+
|
|
+ probe = of_id->data;
|
|
+
|
|
+ return probe(pdev);
|
|
+}
|
|
+
|
|
static struct platform_driver scpsys_drv = {
|
|
.probe = scpsys_probe,
|
|
.driver = {
|