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84acff2865
The original implementation loaded the count register with (wrong) semi- random values due to its implemenation nature. If the wrongly calulated value was below the kickrate, the WD was triggered and rebooted the system. Rework this, partly based on upstream patches, to dynamically fetch the current clockrate and calculate the proper offset for the WD countdown register. Before: [ 143.800000] count val: 27219720 [ 148.820000] count val: 50623201 [ 153.830000] count val: 96425250 [ 158.830000] count val: 89735401 [ 163.840000] count val: 4756110 After: [ 0.700000] MPCore WD init. clockrate: 299984500 prescaler: 256 countrate: 1171814 timeout: 60s [ 358.530000] count val: 35154751 [ 363.540000] count val: 35154750 [ 368.540000] count val: 35154751 [ 373.550000] count val: 35154750 Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com> |
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| .. | ||
| 000-cns3xxx_arch_include.patch | ||
| 001-arm_openwrt_machtypes.patch | ||
| 010-arm_introduce-dma-fiq-irq-broadcast.patch | ||
| 020-watchdog_support.patch | ||
| 025-smp_support.patch | ||
| 030-pcie_clock.patch | ||
| 040-fiq_support.patch | ||
| 045-twd_base.patch | ||
| 055-pcie_io.patch | ||
| 060-pcie_abort.patch | ||
| 065-pcie_skip_inactive.patch | ||
| 070-i2c_support.patch | ||
| 075-spi_support.patch | ||
| 080-sata_support.patch | ||
| 090-timers.patch | ||
| 093-add-virt-pci-io-mapping.patch | ||
| 095-gpio_support.patch | ||
| 097-l2x0_cmdline_disable.patch | ||
| 100-laguna_support.patch | ||
| 101-laguna_sdhci_card_detect.patch | ||
| 110-pci_isolated_interrupts.patch | ||
| 130-Extend-PCIE_BUS_PEER2PEER-to-set-MRSS-128-to-fix-CNS3xxx-BM-DMA..patch | ||
| 200-broadcom_phy_reinit.patch | ||
| 210-dwc2_defaults.patch | ||