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Currently, ipq807x only covers Qualcomm IPQ807x SoC-s. However, Qualcomm also has IPQ60xx and IPQ50xx SoC-s under the AX WiSoC-s and they share a lot of stuff with IPQ807x, especially IPQ60xx so to avoid duplicating kernel patches and everything lets make a common target with per SoC subtargets. Start doing that by renaming ipq807x to qualcommax so that dependencies on ipq807x target can be updated. Signed-off-by: Robert Marko <robimarko@gmail.com>
109 lines
3.3 KiB
Diff
109 lines
3.3 KiB
Diff
From 11592aa862e67f4477dee7e94d5c8244d893de1b Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Sat, 31 Dec 2022 13:03:41 +0100
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Subject: [PATCH] cpufreq: qcom-nvmem: add support for IPQ8074
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IPQ8074 comes in 2 families:
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* IPQ8070A/IPQ8071A (Acorn) up to 1.4GHz
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* IPQ8072A/IPQ8074A/IPQ8076A/IPQ8078A (Hawkeye) up to 2.2GHz
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So, in order to be able to share one OPP table lets add support for IPQ8074
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family based of SMEM SoC ID-s as speedbin fuse is always 0 on IPQ8074.
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IPQ8074 compatible is blacklisted from DT platdev as the cpufreq device
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will get created by NVMEM CPUFreq driver.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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Changes in v2:
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* Print an error if SMEM ID is not part of the IPQ8074 family
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and restrict the speed to Acorn variant (1.4GHz)
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---
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drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
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drivers/cpufreq/qcom-cpufreq-nvmem.c | 43 ++++++++++++++++++++++++++++
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2 files changed, 44 insertions(+)
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--- a/drivers/cpufreq/cpufreq-dt-platdev.c
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+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
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@@ -164,6 +164,7 @@ static const struct of_device_id blockli
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{ .compatible = "ti,omap3", },
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{ .compatible = "qcom,ipq8064", },
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+ { .compatible = "qcom,ipq8074", },
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{ .compatible = "qcom,apq8064", },
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{ .compatible = "qcom,msm8974", },
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{ .compatible = "qcom,msm8960", },
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--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
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+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
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@@ -31,6 +31,9 @@
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#include <dt-bindings/arm/qcom,ids.h>
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+#define IPQ8074_HAWKEYE_VERSION BIT(0)
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+#define IPQ8074_ACORN_VERSION BIT(1)
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+
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struct qcom_cpufreq_drv;
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struct qcom_cpufreq_match_data {
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@@ -204,6 +207,41 @@ len_error:
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return ret;
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}
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+static int qcom_cpufreq_ipq8074_name_version(struct device *cpu_dev,
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+ struct nvmem_cell *speedbin_nvmem,
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+ char **pvs_name,
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+ struct qcom_cpufreq_drv *drv)
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+{
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+ u32 msm_id;
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+ int ret;
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+ *pvs_name = NULL;
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+
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+ ret = qcom_smem_get_soc_id(&msm_id);
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+ if (ret)
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+ return ret;
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+
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+ switch (msm_id) {
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+ case QCOM_ID_IPQ8070A:
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+ case QCOM_ID_IPQ8071A:
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+ drv->versions = IPQ8074_ACORN_VERSION;
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+ break;
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+ case QCOM_ID_IPQ8072A:
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+ case QCOM_ID_IPQ8074A:
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+ case QCOM_ID_IPQ8076A:
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+ case QCOM_ID_IPQ8078A:
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+ drv->versions = IPQ8074_HAWKEYE_VERSION;
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+ break;
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+ default:
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+ dev_err(cpu_dev,
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+ "SoC ID %u is not part of IPQ8074 family, limiting to 1.4GHz!\n",
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+ msm_id);
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+ drv->versions = IPQ8074_ACORN_VERSION;
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+ break;
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+ }
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+
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+ return 0;
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+}
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+
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static const struct qcom_cpufreq_match_data match_data_kryo = {
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.get_version = qcom_cpufreq_kryo_name_version,
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};
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@@ -218,6 +256,10 @@ static const struct qcom_cpufreq_match_d
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.genpd_names = qcs404_genpd_names,
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};
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+static const struct qcom_cpufreq_match_data match_data_ipq8074 = {
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+ .get_version = qcom_cpufreq_ipq8074_name_version,
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+};
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+
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static int qcom_cpufreq_probe(struct platform_device *pdev)
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{
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struct qcom_cpufreq_drv *drv;
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@@ -363,6 +405,7 @@ static const struct of_device_id qcom_cp
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{ .compatible = "qcom,msm8996", .data = &match_data_kryo },
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{ .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
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{ .compatible = "qcom,ipq8064", .data = &match_data_krait },
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+ { .compatible = "qcom,ipq8074", .data = &match_data_ipq8074 },
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{ .compatible = "qcom,apq8064", .data = &match_data_krait },
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{ .compatible = "qcom,msm8974", .data = &match_data_krait },
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{ .compatible = "qcom,msm8960", .data = &match_data_krait },
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