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c98ddf0f01
1. Add support for Marvell CN9130 SoC 2. Add support for CP115,and create an armada-cp11x.dtsi file which will be used to instantiate both CP110 and CP115 3. Add support for AP807/AP807-quad,AP807 is a major component of CN9130 SoC series 4. Drop PCIe I/O ranges from CP11x file and externalize PCIe macros from CP11x file Signed-off-by: Ian Chang <ianchang@ieiworld.com>
136 lines
5.0 KiB
Diff
136 lines
5.0 KiB
Diff
From 1399672e48b573f6526b9ac78cfd50314f0b01a6 Mon Sep 17 00:00:00 2001
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From: Miquel Raynal <miquel.raynal@bootlin.com>
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Date: Fri, 4 Oct 2019 16:27:30 +0200
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Subject: [PATCH] arm64: dts: marvell: Drop PCIe I/O ranges from CP11x file
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As an example, Armada 70x0 and 80x0 SoC 0xf9000000 region points to
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RUNIT/SPICS0 while it is referenced in the DT as PCIe I/O memory
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range. This shows that I/O memory has never been used/working on the
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old SoCs despite the region being advertised. As PCIe I/O ranges will
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not be supported in newer SoCs using CP11x co-processors, let's
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simply drop them. It is not harmful in any case as PCIe device drivers
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can do it all with the regular mapped memory anyway.
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Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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---
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arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 2 --
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.../boot/dts/marvell/armada-8040-mcbin.dtsi | 3 +--
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arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 4 ----
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arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 16 +++-------------
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4 files changed, 4 insertions(+), 21 deletions(-)
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--- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
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+++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
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@@ -19,7 +19,6 @@
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*/
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#define CP11X_NAME cp0
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#define CP11X_BASE f2000000
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-#define CP11X_PCIE_IO_BASE 0xf9000000
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#define CP11X_PCIE_MEM_BASE 0xf6000000
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#define CP11X_PCIE0_BASE f2600000
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#define CP11X_PCIE1_BASE f2620000
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@@ -29,7 +28,6 @@
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#undef CP11X_NAME
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#undef CP11X_BASE
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-#undef CP11X_PCIE_IO_BASE
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#undef CP11X_PCIE_MEM_BASE
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#undef CP11X_PCIE0_BASE
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#undef CP11X_PCIE1_BASE
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--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
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+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
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@@ -179,8 +179,7 @@
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num-lanes = <4>;
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num-viewport = <8>;
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reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>;
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- ranges = <0x81000000 0x0 0xf9010000 0x0 0xf9010000 0x0 0x10000
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- 0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>;
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+ ranges = <0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>;
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phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>,
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<&cp0_comphy2 0>, <&cp0_comphy3 0>;
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phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy",
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--- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
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+++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
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@@ -21,7 +21,6 @@
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*/
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#define CP11X_NAME cp0
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#define CP11X_BASE f2000000
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-#define CP11X_PCIE_IO_BASE 0xf9000000
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#define CP11X_PCIE_MEM_BASE 0xf6000000
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#define CP11X_PCIE0_BASE f2600000
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#define CP11X_PCIE1_BASE f2620000
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@@ -31,7 +30,6 @@
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#undef CP11X_NAME
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#undef CP11X_BASE
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-#undef CP11X_PCIE_IO_BASE
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#undef CP11X_PCIE_MEM_BASE
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#undef CP11X_PCIE0_BASE
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#undef CP11X_PCIE1_BASE
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@@ -42,7 +40,6 @@
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*/
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#define CP11X_NAME cp1
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#define CP11X_BASE f4000000
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-#define CP11X_PCIE_IO_BASE 0xfd000000
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#define CP11X_PCIE_MEM_BASE 0xfa000000
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#define CP11X_PCIE0_BASE f4600000
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#define CP11X_PCIE1_BASE f4620000
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@@ -52,7 +49,6 @@
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#undef CP11X_NAME
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#undef CP11X_BASE
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-#undef CP11X_PCIE_IO_BASE
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#undef CP11X_PCIE_MEM_BASE
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#undef CP11X_PCIE0_BASE
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#undef CP11X_PCIE1_BASE
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--- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
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+++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
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@@ -10,7 +10,6 @@
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#include "armada-common.dtsi"
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-#define CP11X_PCIEx_IO_BASE(iface) (CP11X_PCIE_IO_BASE + (iface * 0x10000))
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#define CP11X_PCIEx_MEM_BASE(iface) (CP11X_PCIE_MEM_BASE + (iface * 0x1000000))
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#define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + 0xf00000)
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@@ -507,11 +506,8 @@
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msi-parent = <&gic_v2m0>;
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bus-range = <0 0xff>;
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- ranges =
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- /* downstream I/O */
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- <0x81000000 0 CP11X_PCIEx_IO_BASE(0) 0 CP11X_PCIEx_IO_BASE(0) 0 0x10000
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/* non-prefetchable memory */
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- 0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 0xf00000>;
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+ ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 0xf00000>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
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@@ -534,11 +530,8 @@
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msi-parent = <&gic_v2m0>;
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bus-range = <0 0xff>;
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- ranges =
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- /* downstream I/O */
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- <0x81000000 0 CP11X_PCIEx_IO_BASE(1) 0 CP11X_PCIEx_IO_BASE(1) 0 0x10000
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/* non-prefetchable memory */
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- 0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 0xf00000>;
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+ ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 0xf00000>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
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@@ -562,11 +555,8 @@
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msi-parent = <&gic_v2m0>;
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bus-range = <0 0xff>;
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- ranges =
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- /* downstream I/O */
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- <0x81000000 0 CP11X_PCIEx_IO_BASE(2) 0 CP11X_PCIEx_IO_BASE(2) 0 0x10000
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/* non-prefetchable memory */
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- 0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 0xf00000>;
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+ ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 0xf00000>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
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