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23deb4ac90
Introduce support for the Qualcomm IPQ60xx SoC. WiFi support still has to be handled and correctly fix hence this is currently marked as source-only to have a solid base to progress on correct support of this and hope Upstream QUIC publish newers ath11k drivers for this SoC. Co-developed-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Mantas Pucka <mantas@8devices.com> [ improve commit description, add SoB for Robert, make it source-only ] Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
33 lines
1.2 KiB
Diff
33 lines
1.2 KiB
Diff
From a120815200adaf3ac28ccf3a1813c78b4be02cc4 Mon Sep 17 00:00:00 2001
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From: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
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Date: Thu, 14 Sep 2023 12:29:59 +0530
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Subject: [PATCH] arm64: dts: qcom: ipq6018: include the GPLL0 as clock
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provider for mailbox
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While the kernel is booting up, APSS PLL will be running at 800MHz with
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GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be
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configured to the rate based on the opp table and the source also will
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be changed to APSS_PLL_EARLY. So allow the mailbox to consume the GPLL0,
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with this inclusion, CPU Freq correctly reports that CPU is running at
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800MHz rather than 24MHz.
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Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
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Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
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---
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arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
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@@ -503,8 +503,8 @@
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compatible = "qcom,ipq6018-apcs-apps-global";
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reg = <0x0 0x0b111000 0x0 0x1000>;
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#clock-cells = <1>;
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- clocks = <&a53pll>, <&xo>;
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- clock-names = "pll", "xo";
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+ clocks = <&a53pll>, <&xo>, <&gcc GPLL0>;
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+ clock-names = "pll", "xo", "gpll0";
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#mbox-cells = <1>;
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};
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