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3a5584e0df
Adds latest 6.6 patches from the Raspberry Pi repository. These patches were generated from: https://github.com/raspberrypi/linux/commits/rpi-6.6.y/ With the following command: git format-patch -N v6.6.67..HEAD (HEAD -> 811ff707533bcd67cdcd368bbd46223082009b12) Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> (cherry picked from commit 692205305db14deeff1a2dc4a6d7f87e19fc418b)
46 lines
1.4 KiB
Diff
46 lines
1.4 KiB
Diff
From 542d0f7f2e9f90fc0f02f8cb141f7c3fbf46081b Mon Sep 17 00:00:00 2001
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From: Dave Stevenson <dave.stevenson@raspberrypi.com>
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Date: Mon, 11 Nov 2024 17:11:18 +0000
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Subject: [PATCH] dt: rp1: Use clk_sys for ethernet hclk and pclk
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hclk and pclk of the MAC are connected to clk_sys, so define
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them as being connected accordingly, rather than having fake
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fixed clocks for them.
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Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
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---
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arch/arm64/boot/dts/broadcom/rp1.dtsi | 15 ++-------------
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1 file changed, 2 insertions(+), 13 deletions(-)
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--- a/arch/arm64/boot/dts/broadcom/rp1.dtsi
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+++ b/arch/arm64/boot/dts/broadcom/rp1.dtsi
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@@ -982,7 +982,8 @@
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <RP1_INT_ETH IRQ_TYPE_LEVEL_HIGH>;
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- clocks = <&macb_pclk &macb_hclk
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+ clocks = <&rp1_clocks RP1_CLK_SYS
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+ &rp1_clocks RP1_CLK_SYS
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&rp1_clocks RP1_CLK_ETH_TSU
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&rp1_clocks RP1_CLK_ETH>;
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clock-names = "pclk", "hclk", "tsu_clk", "tx_clk";
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@@ -1230,18 +1231,6 @@
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clock-output-names = "xosc";
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clock-frequency = <50000000>;
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};
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- macb_pclk: macb_pclk {
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- compatible = "fixed-clock";
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- #clock-cells = <0>;
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- clock-output-names = "pclk";
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- clock-frequency = <200000000>;
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- };
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- macb_hclk: macb_hclk {
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- compatible = "fixed-clock";
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- #clock-cells = <0>;
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- clock-output-names = "hclk";
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- clock-frequency = <200000000>;
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- };
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sdio_src: sdio_src {
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// 400 MHz on FPGA. PLL sys VCO on asic
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compatible = "fixed-clock";
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